[PATCH] D143759: [AMDGPU] Implement whole wave register spill

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

lgtm with nits



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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:70
+    const TargetRegisterClass &RC = AMDGPU::SReg_32_XM0_XEXECRegClass,
+    bool IncludeScratchCopy = true) {
   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
----------------
Documentation comment for what IncludeScratchCopy is


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2218-2219
+      if (IsWWMRegSpill)
+      TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(),
+                                 RS->isRegUsed(AMDGPU::SCC));
       buildSpillLoadStore(
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yassingh wrote:
> arsenm wrote:
> > Indentation's off
> clang format as well arc undos this indentation.
Well it's clearly wrong, so just manually fix it


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2225
+      if (IsWWMRegSpill)
+      TII->restoreExec(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy());
+
----------------
yassingh wrote:
> arsenm wrote:
> > Indentation's off
> same
Well it's clearly wrong, so just manually fix it


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143759/new/

https://reviews.llvm.org/D143759