[PATCH] D143762: [AMDGPU] Enable whole wave register copy

[Yashwant Singh via Phabricator via llvm-commits]

yassingh added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:2419
+SIInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
+  if (MI.getOpcode() == AMDGPU::COPY || MI.getOpcode() == AMDGPU::PRED_COPY)
+    return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
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arsenm wrote:
> Regular copy shouldn't reach here?
Yes it won't, will remove.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:8004
+  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+  if (SrcReg.isVirtual() &&
+      MFI->checkFlag(SrcReg, AMDGPU::VirtRegFlag::WWM_REG))
----------------
arsenm wrote:
> SrcReg.isVirtual should be implied
Added an assert.


================
Comment at: llvm/lib/Target/AMDGPU/SILowerPredicatedCopies.cpp:140
+  bool Changed = false;
+
+  for (MachineBasicBlock &MBB : MF) {
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arsenm wrote:
> Can you early return false if the WWM reg set is empty?
Done, had to add a new helper function.


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Comment at: llvm/lib/Target/AMDGPU/SILowerPredicatedCopies.cpp:159
+        LLVM_DEBUG(dbgs() << "Updated " << MI << " to use COPY opcode");
+        MI.setDesc(TII->get(AMDGPU::COPY));
+        Changed |= true;
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arsenm wrote:
> Do these need to gain an implicit exec use?
Do you mean we should add the implicit exec? In that case, SIFixVGPRCopies will take care?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D143762/new/

https://reviews.llvm.org/D143762