[PATCH] D149775: [AMDGPU] Reserve SGPR pair when long branches are present

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp:86
+    for (const MachineInstr &MI : MBB) {
+      if (MI.isDebugInstr() || MI.isMetaInstruction())
+        continue;
----------------
Just isMetaInstruction is fine, it's a superset of isDebugIstr


================
Comment at: llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp:102
+}
+uint64_t GCNPreRALongBranchReg::getInstrOffset(const MachineInstr &MI) const {
+  const MachineBasicBlock *MBB = MI.getParent();
----------------
Don't need a specific instruction offset, just the block distances are good enough


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149775/new/

https://reviews.llvm.org/D149775