[PATCH] D153499: [RISCV] Add support for custom CSRs for Sifive S76.

[garvit gupta via Phabricator via llvm-commits]

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This patch is a followup of differential D153370 <https://reviews.llvm.org/D153370>

Support for below CSRs is addeed -

1. Branch Prediction Mode CSR
2. Feature Disable CSR
3. Power Dial CSR
4. RNMI CSRs

spec: https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

This patch makes clear distinction between AltName and DeprecatedName. DeprecatedName
is used for  old names which are not in use in latest RISCV spec whereas, AltName
is used when there are multiple registers with same register encoding.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153499

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

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