[PATCH] D153475: [RISCV] Improve SiFive7 for loads and stores

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 21 21:51:08 PDT 2023


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td:399
+  let Latency = 1, ResourceCycles = [Cycles] in
     defm "" : LMULWriteResMX<"WriteVSTE",    [SiFive7VS], mx, IsWorstCase>;
+}
----------------
I don't think we usually indent after `let` if the `let` doesn't use braces.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153475/new/

https://reviews.llvm.org/D153475



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