[PATCH] D153475: [RISCV] Improve SiFive7 for loads and stores

[Michael Maitland via Phabricator via llvm-commits]

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- Unit-stride loads and stores can operate at the full bandwidth of the

memory pipe. The memory pipe is DLEN bits wide.

- Strided loads and stores operate at one element per cycle and should

be scheduled accordingly.

- Indexed loads and stores operate at one element per cycle, and they

stall the machine until all addresses have been generated, so they
cannot be scheduled.

- Unit stride seg2 load is number of DLEN parts

- seg3-8 are one segment per cycle, unless the segment is larger

than DLEN in which each segment takes multiple cycles.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153475

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

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