[PATCH] D153477: [NVPTX] Correctly lower extending loads for fp16 vectors.

[Artem Belevich via Phabricator via llvm-commits]

tra added inline comments.


================
Comment at: llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp:3603
+                                             LoadSDNode *LdNode) {
+  bool IsSigned = LdNode && LdNode->getExtensionType() == ISD::SEXTLOAD;
   switch (SrcTy.SimpleTy) {
----------------
nirvedhmeshram wrote:
> I would like to understand how this is safe, since for target nodes we will always get IsSigned = false . Could there be cases where we would actually need a signed convert?
Good point. 
I'm pretty sure we have not run into any case like these, because in such a case we'd skip extending the types and would end up with the same error we're dealing with now.
Integers appear to follow a somewhat different code path and do not try to do extending load in one instruction.

However, I do not know it for sure, so I'll update the patch to keep behavior for integers unchanged.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153477/new/

https://reviews.llvm.org/D153477