[PATCH] D153477: [NVPTX] Correctly lower extending loads for fp16 vectors.

[Nirvedh Meshram via Phabricator via llvm-commits]

nirvedhmeshram added inline comments.


================
Comment at: llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp:3603
+                                             LoadSDNode *LdNode) {
+  bool IsSigned = LdNode && LdNode->getExtensionType() == ISD::SEXTLOAD;
   switch (SrcTy.SimpleTy) {
----------------
I would like to understand how this is safe, since for target nodes we will always get IsSigned = false . Could there be cases where we would actually need a signed convert?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153477/new/

https://reviews.llvm.org/D153477