[PATCH] D153474: [RISCV] Improve SiFive7 for reductions and ordered reductions

[Michael Maitland via Phabricator via llvm-commits]

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Since the scheduling resources for reductions and ordered reductions now
account for LMUL and SEW, we can modify the Latency and ResourceCycles
for these resoruces.

- Most reductions take a total of approx `vl*SEW/DLEN + 5*(4 + log2(DLEN/SEW))` cycles.
- Ordered floating-point reductions take a total of approx `5*vl` cycles.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153474

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

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