[llvm] 400b3c4 - [ARM] Repair check lines in sub-cmp-peephole.ll test. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 21 14:47:34 PDT 2023
Author: David Green
Date: 2023-06-21T22:47:30+01:00
New Revision: 400b3c47c25b2e88acbd15abf0acf07ed65560b9
URL: https://github.com/llvm/llvm-project/commit/400b3c47c25b2e88acbd15abf0acf07ed65560b9
DIFF: https://github.com/llvm/llvm-project/commit/400b3c47c25b2e88acbd15abf0acf07ed65560b9.diff
LOG: [ARM] Repair check lines in sub-cmp-peephole.ll test. NFC
Commit ec77747fbdca901e0fded58f940dae62e0f6b726 regenerated the check lines
without being very careful about which lines were updated. This attempts to fix
them to make sure the V7 and V8 lines are emitted as needed.
Added:
Modified:
llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
index 68f21b4e96f04..046bbbde68642 100644
--- a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -1,15 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
-; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7
-; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefixes=CHECK,CHECK-V7
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefixes=CHECK,CHECK-V8
define i32 @f(i32 %a, i32 %b) nounwind ssp {
-; V8-LABEL: f:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: subs r0, r0, r1
-; V8-NEXT: movle r0, #0
-; V8-NEXT: bx lr
+; CHECK-LABEL: f:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: subs r0, r0, r1
+; CHECK-NEXT: movle r0, #0
+; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, %b
%sub = sub nsw i32 %a, %b
@@ -18,11 +17,11 @@ entry:
}
define i32 @g(i32 %a, i32 %b) nounwind ssp {
-; V8-LABEL: g:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: subs r0, r1, r0
-; V8-NEXT: movle r0, #0
-; V8-NEXT: bx lr
+; CHECK-LABEL: g:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: subs r0, r1, r0
+; CHECK-NEXT: movle r0, #0
+; CHECK-NEXT: bx lr
entry:
%cmp = icmp slt i32 %a, %b
%sub = sub nsw i32 %b, %a
@@ -31,11 +30,11 @@ entry:
}
define i32 @h(i32 %a, i32 %b) nounwind ssp {
-; V8-LABEL: h:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: subs r0, r0, #3
-; V8-NEXT: movle r0, r1
-; V8-NEXT: bx lr
+; CHECK-LABEL: h:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: subs r0, r0, #3
+; CHECK-NEXT: movle r0, r1
+; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 3
%sub = sub nsw i32 %a, 3
@@ -45,11 +44,11 @@ entry:
; rdar://11725965
define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
-; V8-LABEL: i:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: subs r0, r1, r0
-; V8-NEXT: movls r0, #0
-; V8-NEXT: bx lr
+; CHECK-LABEL: i:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: subs r0, r1, r0
+; CHECK-NEXT: movls r0, #0
+; CHECK-NEXT: bx lr
entry:
%cmp = icmp ult i32 %a, %b
%sub = sub i32 %b, %a
@@ -60,12 +59,12 @@ entry:
; If CPSR is live-out, we can't remove cmp if there exists
; a swapped sub.
define i32 @j(i32 %a, i32 %b) nounwind {
-; V8-LABEL: j:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: subs r1, r0, r1
-; V8-NEXT: movlt r0, r1
-; V8-NEXT: movne r0, r1
-; V8-NEXT: bx lr
+; CHECK-LABEL: j:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: subs r1, r0, r1
+; CHECK-NEXT: movlt r0, r1
+; CHECK-NEXT: movne r0, r1
+; CHECK-NEXT: bx lr
entry:
%cmp = icmp eq i32 %b, %a
%sub = sub nsw i32 %a, %b
@@ -84,16 +83,16 @@ if.else:
; <rdar://problem/12263428>
; Test case from MultiSource/Benchmarks/Ptrdist/bc/number.s
define i32 @bc_raise(i1 %cond) nounwind ssp {
-; V8-LABEL: bc_raise:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: mov r1, #1
-; V8-NEXT: tst r0, #1
-; V8-NEXT: bic r1, r1, r0
-; V8-NEXT: mov r0, #23
-; V8-NEXT: rsbeq r1, r1, #0
-; V8-NEXT: cmp r1, #0
-; V8-NEXT: movweq r0, #17
-; V8-NEXT: bx lr
+; CHECK-LABEL: bc_raise:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r1, #1
+; CHECK-NEXT: tst r0, #1
+; CHECK-NEXT: bic r1, r1, r0
+; CHECK-NEXT: mov r0, #23
+; CHECK-NEXT: rsbeq r1, r1, #0
+; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: movweq r0, #17
+; CHECK-NEXT: bx lr
entry:
%val.2.i = select i1 %cond, i32 0, i32 1
%sub.i = sub nsw i32 0, %val.2.i
@@ -111,13 +110,13 @@ if.end11: ; preds = %num2long.exit
; When considering the producer of cmp's src as the subsuming instruction,
; only consider that when the comparison is to 0.
define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) {
-; V8-LABEL: cmp_src_nonzero:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: sub r0, r0, r1
-; V8-NEXT: cmp r0, #17
-; V8-NEXT: movne r2, r3
-; V8-NEXT: mov r0, r2
-; V8-NEXT: bx lr
+; CHECK-LABEL: cmp_src_nonzero:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: sub r0, r0, r1
+; CHECK-NEXT: cmp r0, #17
+; CHECK-NEXT: movne r2, r3
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: bx lr
entry:
%sub = sub i32 %a, %b
%cmp = icmp eq i32 %sub, 17
@@ -126,14 +125,23 @@ entry:
}
define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
-; V8-LABEL: float_sel:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: vmov s0, r3
-; V8-NEXT: subs r0, r0, r1
-; V8-NEXT: vmov s2, r2
-; V8-NEXT: vseleq.f32 s0, s2, s0
-; V8-NEXT: vmov r0, s0
-; V8-NEXT: bx lr
+; CHECK-V7-LABEL: float_sel:
+; CHECK-V7: @ %bb.0: @ %entry
+; CHECK-V7-NEXT: vmov s2, r2
+; CHECK-V7-NEXT: subs r0, r0, r1
+; CHECK-V7-NEXT: vmov s0, r3
+; CHECK-V7-NEXT: vmoveq.f32 s0, s2
+; CHECK-V7-NEXT: vmov r0, s0
+; CHECK-V7-NEXT: bx lr
+;
+; CHECK-V8-LABEL: float_sel:
+; CHECK-V8: @ %bb.0: @ %entry
+; CHECK-V8-NEXT: vmov s0, r3
+; CHECK-V8-NEXT: subs r0, r0, r1
+; CHECK-V8-NEXT: vmov s2, r2
+; CHECK-V8-NEXT: vseleq.f32 s0, s2, s0
+; CHECK-V8-NEXT: vmov r0, s0
+; CHECK-V8-NEXT: bx lr
entry:
%sub = sub i32 %a, %b
%cmp = icmp eq i32 %sub, 0
@@ -142,14 +150,23 @@ entry:
}
define double @double_sel(i32 %a, i32 %b, double %x, double %y) {
-; V8-LABEL: double_sel:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: vldr d16, [sp]
-; V8-NEXT: vmov d17, r2, r3
-; V8-NEXT: subs r0, r0, r1
-; V8-NEXT: vseleq.f64 d16, d17, d16
-; V8-NEXT: vmov r0, r1, d16
-; V8-NEXT: bx lr
+; CHECK-V7-LABEL: double_sel:
+; CHECK-V7: @ %bb.0: @ %entry
+; CHECK-V7-NEXT: vmov d17, r2, r3
+; CHECK-V7-NEXT: vldr d16, [sp]
+; CHECK-V7-NEXT: subs r0, r0, r1
+; CHECK-V7-NEXT: vmoveq.f64 d16, d17
+; CHECK-V7-NEXT: vmov r0, r1, d16
+; CHECK-V7-NEXT: bx lr
+;
+; CHECK-V8-LABEL: double_sel:
+; CHECK-V8: @ %bb.0: @ %entry
+; CHECK-V8-NEXT: vldr d16, [sp]
+; CHECK-V8-NEXT: vmov d17, r2, r3
+; CHECK-V8-NEXT: subs r0, r0, r1
+; CHECK-V8-NEXT: vseleq.f64 d16, d17, d16
+; CHECK-V8-NEXT: vmov r0, r1, d16
+; CHECK-V8-NEXT: bx lr
entry:
%sub = sub i32 %a, %b
%cmp = icmp eq i32 %sub, 0
@@ -159,20 +176,35 @@ entry:
@t = common global i32 0
define double @double_sub(i32 %a, i32 %b, double %x, double %y) {
-; V8-LABEL: double_sub:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: vldr d16, [sp]
-; V8-NEXT: cmp r0, r1
-; V8-NEXT: vmov d17, r2, r3
-; V8-NEXT: sub r0, r0, r1
-; V8-NEXT: vselgt.f64 d16, d17, d16
-; V8-NEXT: movw r1, :lower16:t
-; V8-NEXT: vmov r2, r3, d16
-; V8-NEXT: movt r1, :upper16:t
-; V8-NEXT: str r0, [r1]
-; V8-NEXT: mov r0, r2
-; V8-NEXT: mov r1, r3
-; V8-NEXT: bx lr
+; CHECK-V7-LABEL: double_sub:
+; CHECK-V7: @ %bb.0: @ %entry
+; CHECK-V7-NEXT: vmov d17, r2, r3
+; CHECK-V7-NEXT: cmp r0, r1
+; CHECK-V7-NEXT: vldr d16, [sp]
+; CHECK-V7-NEXT: sub r0, r0, r1
+; CHECK-V7-NEXT: vmovgt.f64 d16, d17
+; CHECK-V7-NEXT: movw r1, :lower16:t
+; CHECK-V7-NEXT: movt r1, :upper16:t
+; CHECK-V7-NEXT: str r0, [r1]
+; CHECK-V7-NEXT: vmov r2, r3, d16
+; CHECK-V7-NEXT: mov r0, r2
+; CHECK-V7-NEXT: mov r1, r3
+; CHECK-V7-NEXT: bx lr
+;
+; CHECK-V8-LABEL: double_sub:
+; CHECK-V8: @ %bb.0: @ %entry
+; CHECK-V8-NEXT: vldr d16, [sp]
+; CHECK-V8-NEXT: cmp r0, r1
+; CHECK-V8-NEXT: vmov d17, r2, r3
+; CHECK-V8-NEXT: sub r0, r0, r1
+; CHECK-V8-NEXT: vselgt.f64 d16, d17, d16
+; CHECK-V8-NEXT: movw r1, :lower16:t
+; CHECK-V8-NEXT: vmov r2, r3, d16
+; CHECK-V8-NEXT: movt r1, :upper16:t
+; CHECK-V8-NEXT: str r0, [r1]
+; CHECK-V8-NEXT: mov r0, r2
+; CHECK-V8-NEXT: mov r1, r3
+; CHECK-V8-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, %b
%sub = sub i32 %a, %b
@@ -182,20 +214,35 @@ entry:
}
define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) {
-; V8-LABEL: double_sub_swap:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: vldr d16, [sp]
-; V8-NEXT: cmp r1, r0
-; V8-NEXT: vmov d17, r2, r3
-; V8-NEXT: sub r0, r1, r0
-; V8-NEXT: vselge.f64 d16, d16, d17
-; V8-NEXT: movw r1, :lower16:t
-; V8-NEXT: vmov r2, r3, d16
-; V8-NEXT: movt r1, :upper16:t
-; V8-NEXT: str r0, [r1]
-; V8-NEXT: mov r0, r2
-; V8-NEXT: mov r1, r3
-; V8-NEXT: bx lr
+; CHECK-V7-LABEL: double_sub_swap:
+; CHECK-V7: @ %bb.0: @ %entry
+; CHECK-V7-NEXT: vmov d17, r2, r3
+; CHECK-V7-NEXT: cmp r1, r0
+; CHECK-V7-NEXT: vldr d16, [sp]
+; CHECK-V7-NEXT: sub r0, r1, r0
+; CHECK-V7-NEXT: vmovlt.f64 d16, d17
+; CHECK-V7-NEXT: movw r1, :lower16:t
+; CHECK-V7-NEXT: movt r1, :upper16:t
+; CHECK-V7-NEXT: str r0, [r1]
+; CHECK-V7-NEXT: vmov r2, r3, d16
+; CHECK-V7-NEXT: mov r0, r2
+; CHECK-V7-NEXT: mov r1, r3
+; CHECK-V7-NEXT: bx lr
+;
+; CHECK-V8-LABEL: double_sub_swap:
+; CHECK-V8: @ %bb.0: @ %entry
+; CHECK-V8-NEXT: vldr d16, [sp]
+; CHECK-V8-NEXT: cmp r1, r0
+; CHECK-V8-NEXT: vmov d17, r2, r3
+; CHECK-V8-NEXT: sub r0, r1, r0
+; CHECK-V8-NEXT: vselge.f64 d16, d16, d17
+; CHECK-V8-NEXT: movw r1, :lower16:t
+; CHECK-V8-NEXT: vmov r2, r3, d16
+; CHECK-V8-NEXT: movt r1, :upper16:t
+; CHECK-V8-NEXT: str r0, [r1]
+; CHECK-V8-NEXT: mov r0, r2
+; CHECK-V8-NEXT: mov r1, r3
+; CHECK-V8-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, %b
%sub = sub i32 %b, %a
@@ -210,21 +257,21 @@ declare void @exit(i32)
; If the comparison uses the V bit (signed overflow/underflow), we can't
; omit the comparison.
define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
-; V8-LABEL: cmp_slt0:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: .save {r11, lr}
-; V8-NEXT: push {r11, lr}
-; V8-NEXT: movw r0, :lower16:t
-; V8-NEXT: movt r0, :upper16:t
-; V8-NEXT: ldr r0, [r0]
-; V8-NEXT: sub r0, r0, #17
-; V8-NEXT: cmn r0, #1
-; V8-NEXT: ble .LBB11_2
-; V8-NEXT: @ %bb.1: @ %if.else
-; V8-NEXT: mov r0, #0
-; V8-NEXT: bl exit
-; V8-NEXT: .LBB11_2: @ %if.then
-; V8-NEXT: bl abort
+; CHECK-LABEL: cmp_slt0:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: movw r0, :lower16:t
+; CHECK-NEXT: movt r0, :upper16:t
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: sub r0, r0, #17
+; CHECK-NEXT: cmn r0, #1
+; CHECK-NEXT: ble .LBB11_2
+; CHECK-NEXT: @ %bb.1: @ %if.else
+; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: bl exit
+; CHECK-NEXT: .LBB11_2: @ %if.then
+; CHECK-NEXT: bl abort
entry:
%load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
@@ -243,21 +290,21 @@ if.else:
; Same for the C bit. (Note the ult X, 0 is trivially
; false, so the DAG combiner may or may not optimize it).
define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
-; V8-LABEL: cmp_ult0:
-; V8: @ %bb.0: @ %entry
-; V8-NEXT: .save {r11, lr}
-; V8-NEXT: push {r11, lr}
-; V8-NEXT: movw r0, :lower16:t
-; V8-NEXT: movt r0, :upper16:t
-; V8-NEXT: ldr r0, [r0]
-; V8-NEXT: sub r0, r0, #17
-; V8-NEXT: cmp r0, #0
-; V8-NEXT: bhs .LBB12_2
-; V8-NEXT: @ %bb.1: @ %if.then
-; V8-NEXT: bl abort
-; V8-NEXT: .LBB12_2: @ %if.else
-; V8-NEXT: mov r0, #0
-; V8-NEXT: bl exit
+; CHECK-LABEL: cmp_ult0:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: movw r0, :lower16:t
+; CHECK-NEXT: movt r0, :upper16:t
+; CHECK-NEXT: ldr r0, [r0]
+; CHECK-NEXT: sub r0, r0, #17
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: bhs .LBB12_2
+; CHECK-NEXT: @ %bb.1: @ %if.then
+; CHECK-NEXT: bl abort
+; CHECK-NEXT: .LBB12_2: @ %if.else
+; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: bl exit
entry:
%load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
@@ -272,6 +319,4 @@ if.else:
call void @exit(i32 0)
unreachable
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
-; V7: {{.*}}
+
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