[PATCH] D153207: [AArch64] Add patterns for scalar FMUL, FMULX, FMADD, FMSUB

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

There is a lot going on in this patch. It might be good to focus on one of the instructions first. And to split the test changes out into a separate patch, just showing the differences here.



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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:4484
+// Match FMADD instead of indexed FMLA when extracting lane 0.
+let Predicates = [HasFullFP16] in {
+def : Pat<(f16 (any_fma (f16 FPR16:$Rn),
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Could these be in ThreeOperandFPData so that they reuse the patterns with the existing TriOpFrags?


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:6928
 
+// Match indexed FMUL instead of scalar FMUL if it might save a DUP.
+let Predicates = [HasNEON, HasFullFP16] in {
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overmighty wrote:
> For example, this prevents the following regression:
> 
> ```
> define float @test_v3f32(<3 x float> %a) nounwind {
> ; CHECK-LABEL: test_v3f32:
> ; CHECK:       // %bb.0:
> ; CHECK-NEXT:    fmul s1, s0, v0.s[1]
> ; CHECK-NEXT:    fmul s0, s1, v0.s[2]
> ; CHECK-NEXT:    ret
>   %b = call float @llvm.vector.reduce.fmul.f32.v3f32(float 1.0, <3 x float> %a)
>   ret float %b
> }
> ```
> 
> ```
> test_v3f32:                             // @test_v3f32
> // %bb.0:
> 	mov	s1, v0.s[1]
> 	fmul	s1, s1, s0
> 	fmul	s0, s1, v0.s[2]
> 	ret
> ```
Would the same thing happen with other instructions too, if there were tests?


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  https://reviews.llvm.org/D153207/new/

https://reviews.llvm.org/D153207