[PATCH] D153207: [AArch64] Add patterns for scalar FMUL, FMULX, FMADD, FMSUB

[Sam Tebbs via Phabricator via llvm-commits]

samtebbs added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll:444-454
+define dso_local half @t_vmulxh_laneq7_f16(half %a, <8 x half> %b, i32 %lane) {
+; CHECK-LABEL: t_vmulxh_laneq7_f16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fmulx h0, h0, v1.h[7]
+; CHECK-NEXT:    ret
+entry:
+  %extract = extractelement <8 x half> %b, i32 7
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overmighty wrote:
> samtebbs wrote:
> > Some of the test changes, such as this one being moved and renamed, make it hard to see what has changed. Could you try to reduce the number of such differences?
> Sure, I was trying to maintain some kind of consistency. I have also spotted duplicate tests, I don't know if it would be worth it to refactor some of the tests in the future.
Yeah refactoring in a future patch with no functional changes sounds good to me.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153207/new/

https://reviews.llvm.org/D153207