[llvm] c7c71aa - [NFC][AArch64TTI] Breakout add/sub combines into discrete functions.
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 18 05:08:10 PDT 2023
Author: Paul Walker
Date: 2023-06-18T13:07:03+01:00
New Revision: c7c71aa123fdeb520b419ac7daca239902a792ac
URL: https://github.com/llvm/llvm-project/commit/c7c71aa123fdeb520b419ac7daca239902a792ac
DIFF: https://github.com/llvm/llvm-project/commit/c7c71aa123fdeb520b419ac7daca239902a792ac.diff
LOG: [NFC][AArch64TTI] Breakout add/sub combines into discrete functions.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 2a66eab73ab7f..7b587dab2630b 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1282,24 +1282,29 @@ instCombineSVEVectorBinOp(InstCombiner &IC, IntrinsicInst &II) {
static std::optional<Instruction *> instCombineSVEVectorAdd(InstCombiner &IC,
IntrinsicInst &II) {
+ if (auto MLA = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul,
+ Intrinsic::aarch64_sve_mla>(
+ IC, II, true))
+ return MLA;
+ if (auto MAD = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul,
+ Intrinsic::aarch64_sve_mad>(
+ IC, II, false))
+ return MAD;
+ return std::nullopt;
+}
+
+static std::optional<Instruction *>
+instCombineSVEVectorFAdd(InstCombiner &IC, IntrinsicInst &II) {
if (auto FMLA =
instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
Intrinsic::aarch64_sve_fmla>(IC, II,
true))
return FMLA;
- if (auto MLA = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul,
- Intrinsic::aarch64_sve_mla>(
- IC, II, true))
- return MLA;
if (auto FMAD =
instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
Intrinsic::aarch64_sve_fmad>(IC, II,
false))
return FMAD;
- if (auto MAD = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul,
- Intrinsic::aarch64_sve_mad>(
- IC, II, false))
- return MAD;
if (auto FMLA_U =
instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul_u,
Intrinsic::aarch64_sve_fmla_u>(
@@ -1308,17 +1313,33 @@ static std::optional<Instruction *> instCombineSVEVectorAdd(InstCombiner &IC,
return instCombineSVEVectorBinOp(IC, II);
}
-static std::optional<Instruction *> instCombineSVEVectorSub(InstCombiner &IC,
- IntrinsicInst &II) {
+static std::optional<Instruction *>
+instCombineSVEVectorFAddU(InstCombiner &IC, IntrinsicInst &II) {
+ if (auto FMLA =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
+ Intrinsic::aarch64_sve_fmla>(IC, II,
+ true))
+ return FMLA;
+ if (auto FMAD =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
+ Intrinsic::aarch64_sve_fmad>(IC, II,
+ false))
+ return FMAD;
+ if (auto FMLA_U =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul_u,
+ Intrinsic::aarch64_sve_fmla_u>(
+ IC, II, true))
+ return FMLA_U;
+ return instCombineSVEVectorBinOp(IC, II);
+}
+
+static std::optional<Instruction *>
+instCombineSVEVectorFSub(InstCombiner &IC, IntrinsicInst &II) {
if (auto FMLS =
instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
Intrinsic::aarch64_sve_fmls>(IC, II,
true))
return FMLS;
- if (auto MLS = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul,
- Intrinsic::aarch64_sve_mls>(
- IC, II, true))
- return MLS;
if (auto FMSB =
instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
Intrinsic::aarch64_sve_fnmsb>(
@@ -1332,6 +1353,35 @@ static std::optional<Instruction *> instCombineSVEVectorSub(InstCombiner &IC,
return instCombineSVEVectorBinOp(IC, II);
}
+static std::optional<Instruction *>
+instCombineSVEVectorFSubU(InstCombiner &IC, IntrinsicInst &II) {
+ if (auto FMLS =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
+ Intrinsic::aarch64_sve_fmls>(IC, II,
+ true))
+ return FMLS;
+ if (auto FMSB =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
+ Intrinsic::aarch64_sve_fnmsb>(
+ IC, II, false))
+ return FMSB;
+ if (auto FMLS_U =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul_u,
+ Intrinsic::aarch64_sve_fmls_u>(
+ IC, II, true))
+ return FMLS_U;
+ return instCombineSVEVectorBinOp(IC, II);
+}
+
+static std::optional<Instruction *> instCombineSVEVectorSub(InstCombiner &IC,
+ IntrinsicInst &II) {
+ if (auto MLS = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul,
+ Intrinsic::aarch64_sve_mls>(
+ IC, II, true))
+ return MLS;
+ return std::nullopt;
+}
+
static std::optional<Instruction *> instCombineSVEVectorMul(InstCombiner &IC,
IntrinsicInst &II) {
auto *OpPredicate = II.getOperand(0);
@@ -1706,7 +1756,9 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
case Intrinsic::aarch64_sve_fmul_u:
return instCombineSVEVectorMul(IC, II);
case Intrinsic::aarch64_sve_fadd:
+ return instCombineSVEVectorFAdd(IC, II);
case Intrinsic::aarch64_sve_fadd_u:
+ return instCombineSVEVectorFAddU(IC, II);
case Intrinsic::aarch64_sve_add:
return instCombineSVEVectorAdd(IC, II);
case Intrinsic::aarch64_sve_add_u:
@@ -1714,7 +1766,9 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
Intrinsic::aarch64_sve_mla_u>(
IC, II, true);
case Intrinsic::aarch64_sve_fsub:
+ return instCombineSVEVectorFSub(IC, II);
case Intrinsic::aarch64_sve_fsub_u:
+ return instCombineSVEVectorFSubU(IC, II);
case Intrinsic::aarch64_sve_sub:
return instCombineSVEVectorSub(IC, II);
case Intrinsic::aarch64_sve_sub_u:
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