[PATCH] D153155: [RISCV] Remove legacy TA/TU pseudo distiction for VID

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:477
 
-class RISCVMaskedPseudo<bits<4> MaskIdx, bit HasTU = true, bit IsTernary = false> {
+// Describes the relation of a masked psuedu to the unmasked variants.
+// (HasTU = true, IsCombined = false)
----------------
psuedu.-> pseudo


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:485
+//    The unsuffixed version has a merge operand; no explicit _TU variant
+//    exists.  If the unsuffixed version has a policy operand, and can thus
+//    represent all policy states.
----------------
Why does the second sentence start with "If"? Do some instructions in this category not have a policy operand?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1821
       def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>,
-                                   RISCVMaskedPseudo</*MaskOpIdx*/ 1>,
+                                   RISCVMaskedPseudo</*MaskOpIdx*/ 1, /*HasTU=*/false, /*IsCombined=*/true>,
                                    Sched<[WriteVMIdxV_MX, ReadVMask]>;
----------------
Can we wrap this closer to 80 columns?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4311
     let Predicates = GetVTypePredicates<vti>.Predicates in {
       def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
                             (vti.Vector undef),
----------------
I think the undef in this pattern will become IMPLICIT_DEF on its own. Do we need this pattern?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153155/new/

https://reviews.llvm.org/D153155