[PATCH] D153207: [AArch64] Add patterns for scalar FMUL, FMULX, FMADD, FMSUB

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Scalar FMUL, FMULX, FMADD, FMSUB instructions perform better or the same
compared to indexed FMUL, FMULX, FMLA, FMLS.

For example, the Arm Cortex-A55 Software Optimization Guide lists the following
instructions with a throughput of 2 IPC:

- "FP multiply" FMUL
- "ASIMD FP multiply" FMULX
- "FP multiply accumulate" FMADD, FMSUB

whereas it lists the following with a throughput of 1 IPC:

- "ASIMD FP multiply, by element" FMUL, FMULX
- "ASIMD FP multiply accumulate, by element" FMLA, FMLS

The Arm Cortex-A510 Software Optimization Guide, however, does not separately
list "by element" variants of the "ASIMD FP multiply" and "ASIMD FP multiply
accumulate" instructions, which are listed with the same throughput as the
non-ASIMD ones.

Fixes #60817.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153207

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-fma-combines.ll
  llvm/test/CodeGen/AArch64/arm64-fml-combines.ll
  llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
  llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll
  llvm/test/CodeGen/AArch64/arm64-vmul.ll
  llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
  llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll

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