[PATCH] D145211: Relax cross-section branches

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:600
+  /// destination that are in two different text sections.
+  virtual uint64_t getCrossSectionBranchDistance() const {
+    llvm_unreachable("target did not implement");
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I'm surprised this would require a new hook. Does seem like it should take the two blocks or section IDs 

Alternatively could just add blocks to isBranchOffsetInRange?


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:271-273
+  // Get a scratch register. It's important to get a virtual register because
+  // the register scavenger doesn't work with empty blocks.
+  Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
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dhoekwater wrote:
> arsenm wrote:
> > I think it would be better to just fix the scavenger to tolerate empty blocks. 
> Agreed, but I think this would best be done in a different patch. This same approach is used by [AMDGPU/SI](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp#L2556), [RISCV](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp#L1015), and [LoongArch](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp#L389). 
Ugh. Is this even true anymore with backwards scavenging?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D145211/new/

https://reviews.llvm.org/D145211