[llvm] 77e4c48 - [Hexagon] Generate correct instruction for store i1, ($Rs<<$u2 + $Rt)

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2023-06-16T15:26:29-07:00
New Revision: 77e4c48ede4a7ad1e84a78b235578c2aecec6823

URL: https://github.com/llvm/llvm-project/commit/77e4c48ede4a7ad1e84a78b235578c2aecec6823
DIFF: https://github.com/llvm/llvm-project/commit/77e4c48ede4a7ad1e84a78b235578c2aecec6823.diff

LOG: [Hexagon] Generate correct instruction for store i1, ($Rs<<$u2 + $Rt)

Fixes https://github.com/llvm/llvm-project/issues/63359

Added: 
    llvm/test/CodeGen/Hexagon/isel-store-rr-i1.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonPatterns.td

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index bcd98f5df2343..48a79cb9074d6 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -2755,7 +2755,7 @@ let AddedComplexity = 90 in {
   def: Storexr_shl_pat<store,           F64, S4_storerd_rr>;
 
   def: Pat<(store I1:$Pu, (add (shl I32:$Rs, u2_0ImmPred:$u2), I32:$Rt)),
-           (S4_storerb_ur IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>;
+           (S4_storerb_rr IntRegs:$Rt, IntRegs:$Rs, imm:$u2, (I1toI32 I1:$Pu))>;
 }
 
 class SS_<PatFrag F> : SmallStackStore<F>;

diff  --git a/llvm/test/CodeGen/Hexagon/isel-store-rr-i1.ll b/llvm/test/CodeGen/Hexagon/isel-store-rr-i1.ll
new file mode 100644
index 0000000000000..c4a23ab458616
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel-store-rr-i1.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+target triple = "hexagon-unknown-linux-gnu"
+
+define i32 @f0(float %a0, double %a1, i1 %a2, i16 %a3, i8 %a4) {
+; CHECK-LABEL: f0:
+; CHECK:     memb(r1+r0<<#2) = r2
+b0:
+  %v0 = alloca double, align 8
+  %v1 = load i32, ptr poison, align 4
+  %v2 = or i32 42, %v1
+  %v3 = getelementptr ptr, ptr %v0, i32 %v2
+  store i1 false, ptr %v3, align 1
+  ret i32 %v2
+}