[PATCH] D149486: [RISCV] Strengthen atomic ordering for sequentially consistent stores
Paul Kirth via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 16 13:50:12 PDT 2023
paulkirth added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:790
+ "EnableSeqCstTrailingFence",
+ "true",
+ "Enable trailing fence for seq-cst store.">;
----------------
paulkirth wrote:
> I think I set the default wrong here
so .. the behavior I'm observing here seems wrong. Passing `"true"` here actually seems to cause the generated macro to be `GET_SUBTARGETINFO_MACRO(EnableSeqCstTrailingFence, false, enableSeqCstTrailingFence)`, which is what we want, but I would have thought that would only happen if we passed `"false"` here ... am I missing something in how the tablegen is working w/ `SubtargetFeature`?
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https://reviews.llvm.org/D149486/new/
https://reviews.llvm.org/D149486
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