[llvm] 4351060 - [Hexagon] Properly combine overlapping stores in HVC
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 16 13:29:37 PDT 2023
Author: Krzysztof Parzyszek
Date: 2023-06-16T13:29:19-07:00
New Revision: 4351060a2f837dbadc023b18c6deaae3acb26d8f
URL: https://github.com/llvm/llvm-project/commit/4351060a2f837dbadc023b18c6deaae3acb26d8f
DIFF: https://github.com/llvm/llvm-project/commit/4351060a2f837dbadc023b18c6deaae3acb26d8f.diff
LOG: [Hexagon] Properly combine overlapping stores in HVC
Added:
llvm/test/CodeGen/Hexagon/autohvx/vector-align-overapping-stores.ll
Modified:
llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 67aa81df9d461..1424ae2cef71b 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -1355,21 +1355,33 @@ auto AlignVectors::realignStoreGroup(IRBuilderBase &Builder,
// Adjust the store offsets relative to the section start offset.
ByteSpan VSection =
VSpan.section(Index * ScLen, ScLen).shift(-Index * ScLen);
- Value *AccumV = UndefValue::get(SecTy);
- Value *AccumM = HVC.getNullValue(SecTy);
+ Value *Undef = UndefValue::get(SecTy);
+ Value *Zero = HVC.getNullValue(SecTy);
+ Value *AccumV = Undef;
+ Value *AccumM = Zero;
for (ByteSpan::Block &S : VSection) {
Value *Pay = getPayload(S.Seg.Val);
Value *Mask = HVC.rescale(Builder, MakeVec(Builder, getMask(S.Seg.Val)),
Pay->getType(), HVC.getByteTy());
- AccumM = HVC.insertb(Builder, AccumM, HVC.vbytes(Builder, Mask),
- S.Seg.Start, S.Seg.Size, S.Pos);
- AccumV = HVC.insertb(Builder, AccumV, HVC.vbytes(Builder, Pay),
- S.Seg.Start, S.Seg.Size, S.Pos);
+ Value *PartM = HVC.insertb(Builder, Zero, HVC.vbytes(Builder, Mask),
+ S.Seg.Start, S.Seg.Size, S.Pos);
+ AccumM = Builder.CreateOr(AccumM, PartM);
+
+ Value *PartV = HVC.insertb(Builder, Undef, HVC.vbytes(Builder, Pay),
+ S.Seg.Start, S.Seg.Size, S.Pos);
+
+ AccumV = Builder.CreateSelect(
+ Builder.CreateICmp(CmpInst::ICMP_NE, PartM, Zero), PartV, AccumV);
}
ASpanV.Blocks.emplace_back(AccumV, ScLen, Index * ScLen);
ASpanM.Blocks.emplace_back(AccumM, ScLen, Index * ScLen);
}
+ LLVM_DEBUG({
+ dbgs() << "ASpanV before vlalign:\n" << ASpanV << '\n';
+ dbgs() << "ASpanM before vlalign:\n" << ASpanM << '\n';
+ });
+
// vlalign
if (DoAlign) {
for (int Index = 1; Index != NumSectors + 2; ++Index) {
@@ -1381,6 +1393,11 @@ auto AlignVectors::realignStoreGroup(IRBuilderBase &Builder,
}
}
+ LLVM_DEBUG({
+ dbgs() << "ASpanV after vlalign:\n" << ASpanV << '\n';
+ dbgs() << "ASpanM after vlalign:\n" << ASpanM << '\n';
+ });
+
auto createStore = [&](IRBuilderBase &Builder, const ByteSpan &ASpanV,
const ByteSpan &ASpanM, int Index, bool MakePred) {
Value *Val = ASpanV[Index].Seg.Val;
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-overapping-stores.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-overapping-stores.ll
new file mode 100644
index 0000000000000..fc49b8ae391f0
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-overapping-stores.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; RUN: opt -mtriple hexagon -hexagon-vc -hvc-va-full-stores=1 -S < %s | opt -mtriple hexagon -passes=instcombine -S | FileCheck %s
+; Function Attrs: nofree noinline nosync nounwind memory(argmem: readwrite)
+define fastcc void @fred(ptr noalias nocapture align 128 %a0, ptr noalias nocapture readonly align 128 %a1) #0 {
+; CHECK-LABEL: define fastcc void @fred
+; CHECK-SAME: (ptr noalias nocapture align 128 [[A0:%.*]], ptr noalias nocapture readonly align 128 [[A1:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[V0:%.*]] = load <128 x i8>, ptr [[A1]], align 128
+; CHECK-NEXT: store <128 x i8> [[V0]], ptr [[A0]], align 128
+; CHECK-NEXT: ret void
+;
+entry:
+ %v0 = load <128 x i8>, ptr %a1, align 128
+ %v1 = shufflevector <128 x i8> %v0, <128 x i8> poison, <128 x i32> <i32 0, i32 poison, i32 2, i32 poison, i32 4, i32 poison, i32 6, i32 poison, i32 8, i32 poison, i32 10, i32 poison, i32 12, i32 poison, i32 14, i32 poison, i32 16, i32 poison, i32 18, i32 poison, i32 20, i32 poison, i32 22, i32 poison, i32 24, i32 poison, i32 26, i32 poison, i32 28, i32 poison, i32 30, i32 poison, i32 32, i32 poison, i32 34, i32 poison, i32 36, i32 poison, i32 38, i32 poison, i32 40, i32 poison, i32 42, i32 poison, i32 44, i32 poison, i32 46, i32 poison, i32 48, i32 poison, i32 50, i32 poison, i32 52, i32 poison, i32 54, i32 poison, i32 56, i32 poison, i32 58, i32 poison, i32 60, i32 poison, i32 62, i32 poison, i32 64, i32 poison, i32 66, i32 poison, i32 68, i32 poison, i32 70, i32 poison, i32 72, i32 poison, i32 74, i32 poison, i32 76, i32 poison, i32 78, i32 poison, i32 80, i32 poison, i32 82, i32 poison, i32 84, i32 poison, i32 86, i32 poison, i32 88, i32 poison, i32 90, i32 poison, i32 92, i32 poison, i32 94, i32 poison, i32 96, i32 poison, i32 98, i32 poison, i32 100, i32 poison, i32 102, i32 poison, i32 104, i32 poison, i32 106, i32 poison, i32 108, i32 poison, i32 110, i32 poison, i32 112, i32 poison, i32 114, i32 poison, i32 116, i32 poison, i32 118, i32 poison, i32 120, i32 poison, i32 122, i32 poison, i32 124, i32 poison, i32 126, i32 poison>
+ %v2 = shufflevector <128 x i8> %v0, <128 x i8> poison, <128 x i32> <i32 1, i32 poison, i32 3, i32 poison, i32 5, i32 poison, i32 7, i32 poison, i32 9, i32 poison, i32 11, i32 poison, i32 13, i32 poison, i32 15, i32 poison, i32 17, i32 poison, i32 19, i32 poison, i32 21, i32 poison, i32 23, i32 poison, i32 25, i32 poison, i32 27, i32 poison, i32 29, i32 poison, i32 31, i32 poison, i32 33, i32 poison, i32 35, i32 poison, i32 37, i32 poison, i32 39, i32 poison, i32 41, i32 poison, i32 43, i32 poison, i32 45, i32 poison, i32 47, i32 poison, i32 49, i32 poison, i32 51, i32 poison, i32 53, i32 poison, i32 55, i32 poison, i32 57, i32 poison, i32 59, i32 poison, i32 61, i32 poison, i32 63, i32 poison, i32 65, i32 poison, i32 67, i32 poison, i32 69, i32 poison, i32 71, i32 poison, i32 73, i32 poison, i32 75, i32 poison, i32 77, i32 poison, i32 79, i32 poison, i32 81, i32 poison, i32 83, i32 poison, i32 85, i32 poison, i32 87, i32 poison, i32 89, i32 poison, i32 91, i32 poison, i32 93, i32 poison, i32 95, i32 poison, i32 97, i32 poison, i32 99, i32 poison, i32 101, i32 poison, i32 103, i32 poison, i32 105, i32 poison, i32 107, i32 poison, i32 109, i32 poison, i32 111, i32 poison, i32 113, i32 poison, i32 115, i32 poison, i32 117, i32 poison, i32 119, i32 poison, i32 121, i32 poison, i32 123, i32 poison, i32 125, i32 poison, i32 127, i32 poison>
+ tail call void @llvm.masked.store.v128i8.p0(<128 x i8> %v1, ptr %a0, i32 128, <128 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>)
+ %v3 = getelementptr i8, ptr %a0, i32 1
+ tail call void @llvm.masked.store.v128i8.p0(<128 x i8> %v2, ptr %v3, i32 1, <128 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>)
+ ret void
+}
+
+; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: write)
+declare void @llvm.masked.store.v128i8.p0(<128 x i8>, ptr nocapture, i32 immarg, <128 x i1>) #1
+
+attributes #0 = { "target-cpu"="hexagonv68" "target-features"="+hvxv68,+hvx-length128b,+hvx-qfloat,-hvx-ieee-fp" }
+attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: write) }
+
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