[llvm] 11ebe3d - [RISCV] relaxDwarfCallFrameFragment: remove unneeded relocations for relaxation
Volodymyr Sapsai via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 16 12:15:31 PDT 2023
On Jun 16, 2023, at 12:06 PM, Fangrui Song <i at maskray.me> wrote:
>
> On Fri, Jun 16, 2023 at 10:37 AM Volodymyr Sapsai <vsapsai at apple.com> wrote:
>>
>> Hi Fangrui, this change has broken at least bot https://green.lab.llvm.org/green/job/clang-stage1-RA/ (started failing in https://green.lab.llvm.org/green/job/clang-stage1-RA/34684/). Haven’t checked what other bots might be affected.
>>
>> Can you please take a look at this change and revert/fix it?
>
> Sorry for the breakage. I think the root cause is in the
> compiler-rt/lib/xray file. I fixed it in commit
> c57c7b7c99605021123b54c02e57943923874cbe.
>
Sorry, I didn’t know the fix was coming and reverted the change in e872e162a3974e9385b719c0b514190e38845dc5 It’s OK to reapply your change, I haven’t noticed anything wrong with it, just buildbot results.
>> On Jun 15, 2023, at 11:26 PM, Fangrui Song via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>>
>>
>> Author: Fangrui Song
>> Date: 2023-06-15T23:26:25-07:00
>> New Revision: 11ebe3d906558d93a607347de472e7718127f409
>>
>> URL: https://github.com/llvm/llvm-project/commit/11ebe3d906558d93a607347de472e7718127f409
>> DIFF: https://github.com/llvm/llvm-project/commit/11ebe3d906558d93a607347de472e7718127f409.diff
>>
>> LOG: [RISCV] relaxDwarfCallFrameFragment: remove unneeded relocations for relaxation
>>
>> If `evaluateAsAbsolute(Value, Layout.getAssembler())` returns true, we
>> know the address delta is a constant and can suppress relocations
>> (usually SET6/SUB6).
>>
>> While here, replace two evaluateKnownAbsolute calls (subtle; avoid if possible)
>> with evaluateAsAbsolute.
>>
>> Added:
>>
>>
>> Modified:
>> llvm/lib/MC/MCAssembler.cpp
>> llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>> llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
>> llvm/test/MC/ELF/RISCV/gen-dwarf.s
>>
>> Removed:
>>
>>
>>
>> ################################################################################
>> diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp
>> index f1853bfe2b92f..69ea337e16978 100644
>> --- a/llvm/lib/MC/MCAssembler.cpp
>> +++ b/llvm/lib/MC/MCAssembler.cpp
>> @@ -1110,16 +1110,17 @@ bool MCAssembler::relaxDwarfCallFrameFragment(MCAsmLayout &Layout,
>> return WasRelaxed;
>>
>> MCContext &Context = Layout.getAssembler().getContext();
>> - uint64_t OldSize = DF.getContents().size();
>> - int64_t AddrDelta;
>> - bool Abs = DF.getAddrDelta().evaluateKnownAbsolute(AddrDelta, Layout);
>> - assert(Abs && "We created call frame with an invalid expression");
>> - (void) Abs;
>> + int64_t Value;
>> + bool Abs = DF.getAddrDelta().evaluateAsAbsolute(Value, Layout);
>> + assert(Abs && "CFA with invalid expression");
>> + (void)Abs;
>> +
>> SmallVectorImpl<char> &Data = DF.getContents();
>> + uint64_t OldSize = Data.size();
>> Data.clear();
>> DF.getFixups().clear();
>>
>> - MCDwarfFrameEmitter::encodeAdvanceLoc(Context, AddrDelta, Data);
>> + MCDwarfFrameEmitter::encodeAdvanceLoc(Context, Value, Data);
>> return OldSize != Data.size();
>> }
>>
>>
>> diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>> index 68dfb6852631c..81542b2697d5f 100644
>> --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>> +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>> @@ -273,14 +273,15 @@ bool RISCVAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF,
>> bool RISCVAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF,
>> MCAsmLayout &Layout,
>> bool &WasRelaxed) const {
>> -
>> const MCExpr &AddrDelta = DF.getAddrDelta();
>> SmallVectorImpl<char> &Data = DF.getContents();
>> SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
>> size_t OldSize = Data.size();
>>
>> int64_t Value;
>> - bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
>> + if (AddrDelta.evaluateAsAbsolute(Value, Layout.getAssembler()))
>> + return false;
>> + bool IsAbsolute = AddrDelta.evaluateAsAbsolute(Value, Layout);
>> assert(IsAbsolute && "CFA with invalid expression");
>> (void)IsAbsolute;
>>
>>
>> diff --git a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
>> index 557986fa38b56..280da01567a2b 100644
>> --- a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
>> +++ b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
>> @@ -7,15 +7,29 @@
>> ; RELAX-NEXT: 0x1C R_RISCV_32_PCREL - 0x0
>> ; RELAX-NEXT: 0x20 R_RISCV_ADD32 - 0x0
>> ; RELAX-NEXT: 0x20 R_RISCV_SUB32 - 0x0
>> -; RELAX-NOT: }
>> -; RELAX: 0x39 R_RISCV_SET6 - 0x0
>> -; RELAX-NEXT: 0x39 R_RISCV_SUB6 - 0x0
>> -;
>> +; RELAX-NEXT: 0x30 R_RISCV_32_PCREL - 0x0
>> +; RELAX-NEXT: 0x34 R_RISCV_ADD32 - 0x0
>> +; RELAX-NEXT: 0x34 R_RISCV_SUB32 - 0x0
>> +; RELAX-NEXT: 0x44 R_RISCV_32_PCREL - 0x0
>> +; RELAX-NEXT: 0x48 R_RISCV_ADD32 - 0x0
>> +; RELAX-NEXT: 0x48 R_RISCV_SUB32 - 0x0
>> +; RELAX-NEXT: }
>> +
>> ; RELAX-DWARFDUMP-NOT: error: failed to compute relocation
>> -; RELAX-DWARFDUMP: CIE
>> -; RELAX-DWARFDUMP: DW_CFA_advance_loc
>> -; RELAX-DWARFDUMP: DW_CFA_def_cfa_offset
>> -; RELAX-DWARFDUMP: DW_CFA_offset
>> +; RELAX-DWARFDUMP: FDE
>> +; RELAX-DWARFDUMP-NEXT: Format:
>> +; RELAX-DWARFDUMP: DW_CFA_advance_loc: 4
>> +; RELAX-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +16
>> +; RELAX-DWARFDUMP-EMPTY:
>> +
>> +; RELAX-DWARFDUMP: FDE
>> +; RELAX-DWARFDUMP: Format:
>> +; RELAX-DWARFDUMP-NEXT: DW_CFA_advance_loc: 4
>> +; RELAX-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +16
>> +; RELAX-DWARFDUMP-NEXT: DW_CFA_advance_loc: 4
>> +; RELAX-DWARFDUMP-NEXT: DW_CFA_offset: X1 -4
>> +; RELAX-DWARFDUMP-NEXT: DW_CFA_nop
>> +; RELAX-DWARFDUMP-EMPTY:
>> source_filename = "frame.c"
>>
>> ; Function Attrs: noinline nounwind optnone
>>
>> diff --git a/llvm/test/MC/ELF/RISCV/gen-dwarf.s b/llvm/test/MC/ELF/RISCV/gen-dwarf.s
>> index a9e9d2c730bbb..c0c8cae61c72b 100644
>> --- a/llvm/test/MC/ELF/RISCV/gen-dwarf.s
>> +++ b/llvm/test/MC/ELF/RISCV/gen-dwarf.s
>> @@ -45,8 +45,6 @@
>> # RELOC-NEXT: 0x20 R_RISCV_SUB32 - 0x0
>> # RELOC-NEXT: 0x25 R_RISCV_SET6 - 0x0
>> # RELOC-NEXT: 0x25 R_RISCV_SUB6 - 0x0
>> -# RELOC-NEXT: 0x28 R_RISCV_SET6 - 0x0
>> -# RELOC-NEXT: 0x28 R_RISCV_SUB6 - 0x0
>> # RELOC-NEXT: 0x34 R_RISCV_32_PCREL - 0x0
>> # RELOC-NEXT: 0x38 R_RISCV_ADD32 - 0x0
>> # RELOC-NEXT: 0x38 R_RISCV_SUB32 - 0x0
>>
>>
>>
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