[llvm] ec77747 - [NFC] Autogenerate CodeGen/ARM/sub-cmp-peephole.ll
Amaury Séchet via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 16 08:15:35 PDT 2023
Author: Amaury Séchet
Date: 2023-06-16T15:14:47Z
New Revision: ec77747fbdca901e0fded58f940dae62e0f6b726
URL: https://github.com/llvm/llvm-project/commit/ec77747fbdca901e0fded58f940dae62e0f6b726
DIFF: https://github.com/llvm/llvm-project/commit/ec77747fbdca901e0fded58f940dae62e0f6b726.diff
LOG: [NFC] Autogenerate CodeGen/ARM/sub-cmp-peephole.ll
Added:
Modified:
llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
index 7e3b8b24424ad..68f21b4e96f04 100644
--- a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -1,13 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8
define i32 @f(i32 %a, i32 %b) nounwind ssp {
+; V8-LABEL: f:
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: subs r0, r0, r1
+; V8-NEXT: movle r0, #0
+; V8-NEXT: bx lr
entry:
-; CHECK-LABEL: f:
-; CHECK: subs
-; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, %b
%sub = sub nsw i32 %a, %b
%sub. = select i1 %cmp, i32 %sub, i32 0
@@ -15,10 +18,12 @@ entry:
}
define i32 @g(i32 %a, i32 %b) nounwind ssp {
+; V8-LABEL: g:
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: subs r0, r1, r0
+; V8-NEXT: movle r0, #0
+; V8-NEXT: bx lr
entry:
-; CHECK-LABEL: g:
-; CHECK: subs
-; CHECK-NOT: cmp
%cmp = icmp slt i32 %a, %b
%sub = sub nsw i32 %b, %a
%sub. = select i1 %cmp, i32 %sub, i32 0
@@ -26,10 +31,12 @@ entry:
}
define i32 @h(i32 %a, i32 %b) nounwind ssp {
+; V8-LABEL: h:
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: subs r0, r0, #3
+; V8-NEXT: movle r0, r1
+; V8-NEXT: bx lr
entry:
-; CHECK-LABEL: h:
-; CHECK: subs
-; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, 3
%sub = sub nsw i32 %a, 3
%sub. = select i1 %cmp, i32 %sub, i32 %b
@@ -38,22 +45,28 @@ entry:
; rdar://11725965
define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
+; V8-LABEL: i:
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: subs r0, r1, r0
+; V8-NEXT: movls r0, #0
+; V8-NEXT: bx lr
entry:
-; CHECK-LABEL: i:
-; CHECK: subs
-; CHECK-NOT: cmp
%cmp = icmp ult i32 %a, %b
%sub = sub i32 %b, %a
%sub. = select i1 %cmp, i32 %sub, i32 0
ret i32 %sub.
}
+
; If CPSR is live-out, we can't remove cmp if there exists
; a swapped sub.
define i32 @j(i32 %a, i32 %b) nounwind {
+; V8-LABEL: j:
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: subs r1, r0, r1
+; V8-NEXT: movlt r0, r1
+; V8-NEXT: movne r0, r1
+; V8-NEXT: bx lr
entry:
-; CHECK-LABEL: j:
-; CHECK: sub
-; CHECK: cmp
%cmp = icmp eq i32 %b, %a
%sub = sub nsw i32 %a, %b
br i1 %cmp, label %if.then, label %if.else
@@ -70,10 +83,17 @@ if.else:
; If the sub/rsb instruction is predicated, we can't use the flags.
; <rdar://problem/12263428>
; Test case from MultiSource/Benchmarks/Ptrdist/bc/number.s
-; CHECK: bc_raise
-; CHECK: rsbeq
-; CHECK: cmp
define i32 @bc_raise(i1 %cond) nounwind ssp {
+; V8-LABEL: bc_raise:
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: mov r1, #1
+; V8-NEXT: tst r0, #1
+; V8-NEXT: bic r1, r1, r0
+; V8-NEXT: mov r0, #23
+; V8-NEXT: rsbeq r1, r1, #0
+; V8-NEXT: cmp r1, #0
+; V8-NEXT: movweq r0, #17
+; V8-NEXT: bx lr
entry:
%val.2.i = select i1 %cond, i32 0, i32 1
%sub.i = sub nsw i32 0, %val.2.i
@@ -91,10 +111,14 @@ if.end11: ; preds = %num2long.exit
; When considering the producer of cmp's src as the subsuming instruction,
; only consider that when the comparison is to 0.
define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) {
+; V8-LABEL: cmp_src_nonzero:
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: sub r0, r0, r1
+; V8-NEXT: cmp r0, #17
+; V8-NEXT: movne r2, r3
+; V8-NEXT: mov r0, r2
+; V8-NEXT: bx lr
entry:
-; CHECK-LABEL: cmp_src_nonzero:
-; CHECK: sub
-; CHECK: cmp
%sub = sub i32 %a, %b
%cmp = icmp eq i32 %sub, 17
%ret = select i1 %cmp, i32 %x, i32 %y
@@ -102,12 +126,15 @@ entry:
}
define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
-entry:
-; CHECK-LABEL: float_sel:
-; CHECK-NOT: cmp
; V8-LABEL: float_sel:
-; V8-NOT: cmp
-; V8: vseleq.f32
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: vmov s0, r3
+; V8-NEXT: subs r0, r0, r1
+; V8-NEXT: vmov s2, r2
+; V8-NEXT: vseleq.f32 s0, s2, s0
+; V8-NEXT: vmov r0, s0
+; V8-NEXT: bx lr
+entry:
%sub = sub i32 %a, %b
%cmp = icmp eq i32 %sub, 0
%ret = select i1 %cmp, float %x, float %y
@@ -115,12 +142,15 @@ entry:
}
define double @double_sel(i32 %a, i32 %b, double %x, double %y) {
-entry:
-; CHECK-LABEL: double_sel:
-; CHECK-NOT: cmp
; V8-LABEL: double_sel:
-; V8-NOT: cmp
-; V8: vseleq.f64
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: vldr d16, [sp]
+; V8-NEXT: vmov d17, r2, r3
+; V8-NEXT: subs r0, r0, r1
+; V8-NEXT: vseleq.f64 d16, d17, d16
+; V8-NEXT: vmov r0, r1, d16
+; V8-NEXT: bx lr
+entry:
%sub = sub i32 %a, %b
%cmp = icmp eq i32 %sub, 0
%ret = select i1 %cmp, double %x, double %y
@@ -129,12 +159,21 @@ entry:
@t = common global i32 0
define double @double_sub(i32 %a, i32 %b, double %x, double %y) {
-entry:
-; CHECK-LABEL: double_sub:
-; CHECK: subs
-; CHECK-NOT: cmp
; V8-LABEL: double_sub:
-; V8: vsel
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: vldr d16, [sp]
+; V8-NEXT: cmp r0, r1
+; V8-NEXT: vmov d17, r2, r3
+; V8-NEXT: sub r0, r0, r1
+; V8-NEXT: vselgt.f64 d16, d17, d16
+; V8-NEXT: movw r1, :lower16:t
+; V8-NEXT: vmov r2, r3, d16
+; V8-NEXT: movt r1, :upper16:t
+; V8-NEXT: str r0, [r1]
+; V8-NEXT: mov r0, r2
+; V8-NEXT: mov r1, r3
+; V8-NEXT: bx lr
+entry:
%cmp = icmp sgt i32 %a, %b
%sub = sub i32 %a, %b
store i32 %sub, ptr @t
@@ -143,14 +182,21 @@ entry:
}
define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) {
-entry:
-; V7-LABEL: double_sub_swap:
-; V7-NOT: cmp
-; V7: subs
; V8-LABEL: double_sub_swap:
-; V8-NOT: subs
-; V8: cmp
-; V8: vsel
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: vldr d16, [sp]
+; V8-NEXT: cmp r1, r0
+; V8-NEXT: vmov d17, r2, r3
+; V8-NEXT: sub r0, r1, r0
+; V8-NEXT: vselge.f64 d16, d16, d17
+; V8-NEXT: movw r1, :lower16:t
+; V8-NEXT: vmov r2, r3, d16
+; V8-NEXT: movt r1, :upper16:t
+; V8-NEXT: str r0, [r1]
+; V8-NEXT: mov r0, r2
+; V8-NEXT: mov r1, r3
+; V8-NEXT: bx lr
+entry:
%cmp = icmp sgt i32 %a, %b
%sub = sub i32 %b, %a
%ret = select i1 %cmp, double %x, double %y
@@ -164,11 +210,22 @@ declare void @exit(i32)
; If the comparison uses the V bit (signed overflow/underflow), we can't
; omit the comparison.
define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
+; V8-LABEL: cmp_slt0:
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: .save {r11, lr}
+; V8-NEXT: push {r11, lr}
+; V8-NEXT: movw r0, :lower16:t
+; V8-NEXT: movt r0, :upper16:t
+; V8-NEXT: ldr r0, [r0]
+; V8-NEXT: sub r0, r0, #17
+; V8-NEXT: cmn r0, #1
+; V8-NEXT: ble .LBB11_2
+; V8-NEXT: @ %bb.1: @ %if.else
+; V8-NEXT: mov r0, #0
+; V8-NEXT: bl exit
+; V8-NEXT: .LBB11_2: @ %if.then
+; V8-NEXT: bl abort
entry:
-; CHECK-LABEL: cmp_slt0
-; CHECK: sub
-; CHECK: cmn
-; CHECK: ble
%load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
%cmp = icmp slt i32 %sub, 0
@@ -186,11 +243,22 @@ if.else:
; Same for the C bit. (Note the ult X, 0 is trivially
; false, so the DAG combiner may or may not optimize it).
define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
+; V8-LABEL: cmp_ult0:
+; V8: @ %bb.0: @ %entry
+; V8-NEXT: .save {r11, lr}
+; V8-NEXT: push {r11, lr}
+; V8-NEXT: movw r0, :lower16:t
+; V8-NEXT: movt r0, :upper16:t
+; V8-NEXT: ldr r0, [r0]
+; V8-NEXT: sub r0, r0, #17
+; V8-NEXT: cmp r0, #0
+; V8-NEXT: bhs .LBB12_2
+; V8-NEXT: @ %bb.1: @ %if.then
+; V8-NEXT: bl abort
+; V8-NEXT: .LBB12_2: @ %if.else
+; V8-NEXT: mov r0, #0
+; V8-NEXT: bl exit
entry:
-; CHECK-LABEL: cmp_ult0
-; CHECK: sub
-; CHECK: cmp
-; CHECK: bhs
%load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
%cmp = icmp ult i32 %sub, 0
@@ -204,3 +272,6 @@ if.else:
call void @exit(i32 0)
unreachable
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
+; V7: {{.*}}
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