[PATCH] D152928: [RFC][DAG] Initially add nodes in the worklist in topological order.

Amaury SECHET via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jun 16 06:41:16 PDT 2023 

deadalnix updated this revision to Diff 532126.
deadalnix added a comment.
Herald added subscribers: wangpc, luke, pmatos, asb, frasercrmck, zzheng, kerbowa, luismarques, apazos, sameer.abuasal, s.egerton, dmgreen, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, edward-jones, MaskRay, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, fedor.sergeev, aheejin, jgravelle-google, sbc100, jvesely, sdardis, jyknight, dschuff, qcolombet.

Fix numerous tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152928/new/

https://reviews.llvm.org/D152928

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-outline_atomics.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-rcpc.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-v8a.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
  llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
  llvm/test/CodeGen/AArch64/aarch64-addv.ll
  llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
  llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
  llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
  llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
  llvm/test/CodeGen/AArch64/addr-of-ret-addr.ll
  llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
  llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
  llvm/test/CodeGen/AArch64/arm64-build-vector.ll
  llvm/test/CodeGen/AArch64/arm64-ccmp.ll
  llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll
  llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
  llvm/test/CodeGen/AArch64/arm64-ld-from-st.ll
  llvm/test/CodeGen/AArch64/arm64-memcpy-inline.ll
  llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
  llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
  llvm/test/CodeGen/AArch64/arm64-neon-vector-shuffle-extract.ll
  llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
  llvm/test/CodeGen/AArch64/arm64-rev.ll
  llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/arm64-vhadd.ll
  llvm/test/CodeGen/AArch64/arm64-virtual_base.ll
  llvm/test/CodeGen/AArch64/arm64-vmul.ll
  llvm/test/CodeGen/AArch64/arm64-windows-calls.ll
  llvm/test/CodeGen/AArch64/arm64-xaluo.ll
  llvm/test/CodeGen/AArch64/arm64_32-neon.ll
  llvm/test/CodeGen/AArch64/arm64_32.ll
  llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
  llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
  llvm/test/CodeGen/AArch64/bcmp.ll
  llvm/test/CodeGen/AArch64/bfis-in-loop.ll
  llvm/test/CodeGen/AArch64/bitfield-insert.ll
  llvm/test/CodeGen/AArch64/build-vector-to-extract-subvec-crash.ll
  llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
  llvm/test/CodeGen/AArch64/cmp-bool.ll
  llvm/test/CodeGen/AArch64/cmp-const-max.ll
  llvm/test/CodeGen/AArch64/combine-andintoload.ll
  llvm/test/CodeGen/AArch64/combine-mul.ll
  llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
  llvm/test/CodeGen/AArch64/dag-ReplaceAllUsesOfValuesWith.ll
  llvm/test/CodeGen/AArch64/dag-combine-mul-shl.ll
  llvm/test/CodeGen/AArch64/dag-combine-select.ll
  llvm/test/CodeGen/AArch64/expand-select.ll
  llvm/test/CodeGen/AArch64/fadd-combines.ll
  llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
  llvm/test/CodeGen/AArch64/fold-global-offsets.ll
  llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
  llvm/test/CodeGen/AArch64/fpclamptosat.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/funnel-shift.ll
  llvm/test/CodeGen/AArch64/icmp-shift-opt.ll
  llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
  llvm/test/CodeGen/AArch64/insertshuffleload.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
  llvm/test/CodeGen/AArch64/neon-abd.ll
  llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
  llvm/test/CodeGen/AArch64/neon-dotreduce.ll
  llvm/test/CodeGen/AArch64/neon-sad.ll
  llvm/test/CodeGen/AArch64/nontemporal-load.ll
  llvm/test/CodeGen/AArch64/nzcv-save.ll
  llvm/test/CodeGen/AArch64/pr61111.ll
  llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll
  llvm/test/CodeGen/AArch64/pull-negations-after-concat-of-truncates.ll
  llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
  llvm/test/CodeGen/AArch64/reduce-shuffle.ll
  llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll
  llvm/test/CodeGen/AArch64/rotate-extract.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/sat-add.ll
  llvm/test/CodeGen/AArch64/select_fmf.ll
  llvm/test/CodeGen/AArch64/setcc-fsh.ll
  llvm/test/CodeGen/AArch64/shift-accumulate.ll
  llvm/test/CodeGen/AArch64/shift-amount-mod.ll
  llvm/test/CodeGen/AArch64/shift-by-signext.ll
  llvm/test/CodeGen/AArch64/shiftregister-from-and.ll
  llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
  llvm/test/CodeGen/AArch64/signbit-shift.ll
  llvm/test/CodeGen/AArch64/signbit-test.ll
  llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll
  llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
  llvm/test/CodeGen/AArch64/srem-lkk.ll
  llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
  llvm/test/CodeGen/AArch64/srem-seteq.ll
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll
  llvm/test/CodeGen/AArch64/sve-aba.ll
  llvm/test/CodeGen/AArch64/sve-abd.ll
  llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-bitcast.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fcopysign.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-compares.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-fma.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
  llvm/test/CodeGen/AArch64/sve-fixed-vector-zext.ll
  llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
  llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
  llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
  llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
  llvm/test/CodeGen/AArch64/sve-vl-arith.ll
  llvm/test/CodeGen/AArch64/sve-vscale-attr.ll
  llvm/test/CodeGen/AArch64/sve2-fixed-length-fcopysign.ll
  llvm/test/CodeGen/AArch64/swifterror.ll
  llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
  llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
  llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
  llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
  llvm/test/CodeGen/AArch64/urem-seteq.ll
  llvm/test/CodeGen/AArch64/ushl_sat.ll
  llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-add.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
  llvm/test/CodeGen/AArch64/wide-scalar-shift-by-byte-multiple-legalization.ll
  llvm/test/CodeGen/AArch64/wide-scalar-shift-legalization.ll
  llvm/test/CodeGen/AArch64/zext-to-tbl.ll
  llvm/test/CodeGen/AMDGPU/carryout-selection.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/store-local.96.ll
  llvm/test/CodeGen/Mips/atomic.ll
  llvm/test/CodeGen/Mips/cconv/byval.ll
  llvm/test/CodeGen/Mips/cconv/vector.ll
  llvm/test/CodeGen/Mips/dins.ll
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  llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll
  llvm/test/CodeGen/Mips/mips64-f128.ll
  llvm/test/CodeGen/Mips/o32_cc_byval.ll
  llvm/test/CodeGen/Mips/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/Mips/v2i16tof32.ll
  llvm/test/CodeGen/RISCV/rvv/combine-store.ll
  llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
  llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-vslide1down.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-vslide1up.ll
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  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
  (711 more files...)

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