[PATCH] D152714: [AArch64][Optimization]Solving the FCCMP issue
Priyanshi Agarwal via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 16 00:16:43 PDT 2023
ipriyanshi1708 updated this revision to Diff 532009.
ipriyanshi1708 added a comment.
Generated the desired assembly
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152714/new/
https://reviews.llvm.org/D152714
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16391,6 +16391,23 @@
if (SDValue R = performANDORCSELCombine(N, DAG))
return R;
+ SDLoc DL(N);
+ AArch64CC::CondCode AArch64CC;
+ SDValue Cmp,Cset;
+
+ if (!DCI.isBeforeLegalize() &&
+ (Cmp = emitConjunction(DAG, SDValue(N, 0), AArch64CC))){
+
+ unsigned ZeroReg = VT.getSizeInBits() == 32 ? AArch64::WZR : AArch64::XZR;
+ AArch64CC::CondCode InvertedCC = AArch64CC::getInvertedCondCode(AArch64CC);
+
+ Cset = DAG.getNode(AArch64ISD::CSINC, DL, VT,
+ DAG.getRegister(ZeroReg, VT), DAG.getRegister(ZeroReg, VT),
+ DAG.getConstant(InvertedCC, DL, MVT::i32), Cmp);
+
+ return Cset;
+ }
+
if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
return SDValue();
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