[PATCH] D152993: [VP][RISCV] Add vp..is.fpclass and RISC-V support

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Need Verifier.cpp to make sure only legal bits are set. See existing code for llvm.is.fpclass.



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Comment at: llvm/include/llvm/IR/Intrinsics.td:2006
                                llvm_i32_ty]>;
+  def int_vp_is_fpclass: DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
+                              [ llvm_anyvector_ty,
----------------
`DefaultAttrsIntrinsics<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],`


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:7929
+    SDNodeFlags SDFlags;
+    if (auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
+      SDFlags.copyFMF(*FPMO);
----------------
We don't copy fast math flags for llvm.is.fpclass. Why do we copy them here?


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Comment at: llvm/lib/IR/IntrinsicInst.cpp:626
+    VPFunc = Intrinsic::getDeclaration(
+        M, VPID, {ReturnType, Params[0]->getType(), Params[2]->getType()});
+    break;
----------------
I think there are too many types here? Only two `any` types exist in the definition. And if we use `LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>` for the destination, we only need one.


Repository:
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  https://reviews.llvm.org/D152993/new/

https://reviews.llvm.org/D152993