[PATCH] D153101: [SPIR-V] Simplify regclasses hierarchy and cleanup regbanks

[Aleksandr Bezzubikov via Phabricator via llvm-commits]

zuban32 created this revision.
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The subset of SPIR-V instructions we have a dag pattern for
allows us to distinguish between integer and float versions
of instructions basing on existing constraints (different
GMIR opcodes for integer/FP versions of instructions + type inference),
so FP regclasses are redundant and can be removed.

And since SPIR-V is a virtual ISA it only needs a single regbank
to support instruction selection.

Depends on D153099 <https://reviews.llvm.org/D153099> and D153100 <https://reviews.llvm.org/D153100>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153101

Files:
  llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
  llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
  llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
  llvm/lib/Target/SPIRV/SPIRVRegisterBankInfo.cpp
  llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
  llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td

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