[llvm] aa2d0fb - [MC] Add MCRegisterInfo::regunits for iteration over register units
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 15 19:40:08 PDT 2023
Author: Sergei Barannikov
Date: 2023-06-16T05:39:50+03:00
New Revision: aa2d0fbc30d948dc9ce7d312ae4c56467fa57932
URL: https://github.com/llvm/llvm-project/commit/aa2d0fbc30d948dc9ce7d312ae4c56467fa57932
DIFF: https://github.com/llvm/llvm-project/commit/aa2d0fbc30d948dc9ce7d312ae4c56467fa57932.diff
LOG: [MC] Add MCRegisterInfo::regunits for iteration over register units
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D152098
Added:
Modified:
llvm/include/llvm/CodeGen/LiveIntervals.h
llvm/include/llvm/CodeGen/LiveRegUnits.h
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/include/llvm/MC/MCRegister.h
llvm/include/llvm/MC/MCRegisterInfo.h
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/BreakFalseDeps.cpp
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/InterferenceCache.cpp
llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
llvm/lib/CodeGen/LiveIntervals.cpp
llvm/lib/CodeGen/LiveRegMatrix.cpp
llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp
llvm/lib/CodeGen/MachineCopyPropagation.cpp
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/MachineTraceMetrics.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/CodeGen/PrologEpilogInserter.cpp
llvm/lib/CodeGen/RDFRegisters.cpp
llvm/lib/CodeGen/ReachingDefAnalysis.cpp
llvm/lib/CodeGen/RegAllocBasic.cpp
llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegAllocPBQP.cpp
llvm/lib/CodeGen/RegisterCoalescer.cpp
llvm/lib/CodeGen/RegisterPressure.cpp
llvm/lib/CodeGen/RegisterScavenging.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/lib/CodeGen/VirtRegMap.cpp
llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
llvm/unittests/MI/LiveIntervalTest.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/LiveIntervals.h b/llvm/include/llvm/CodeGen/LiveIntervals.h
index f972dd0136c73..3b3a4e12f7940 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervals.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervals.h
@@ -417,8 +417,8 @@ class VirtRegMap;
/// method can result in inconsistent liveness tracking if multiple phyical
/// registers share a regunit, and should be used cautiously.
void removeAllRegUnitsForPhysReg(MCRegister Reg) {
- for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
- removeRegUnit(*Units);
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ removeRegUnit(Unit);
}
/// Remove value numbers and related live segments starting at position
diff --git a/llvm/include/llvm/CodeGen/LiveRegUnits.h b/llvm/include/llvm/CodeGen/LiveRegUnits.h
index a5a8fc6d92a37..a750d5dec5463 100644
--- a/llvm/include/llvm/CodeGen/LiveRegUnits.h
+++ b/llvm/include/llvm/CodeGen/LiveRegUnits.h
@@ -84,8 +84,8 @@ class LiveRegUnits {
/// Adds register units covered by physical register \p Reg.
void addReg(MCPhysReg Reg) {
- for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
- Units.set(*Unit);
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ Units.set(Unit);
}
/// Adds register units covered by physical register \p Reg that are
@@ -100,8 +100,8 @@ class LiveRegUnits {
/// Removes all register units covered by physical register \p Reg.
void removeReg(MCPhysReg Reg) {
- for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
- Units.reset(*Unit);
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ Units.reset(Unit);
}
/// Removes register units not preserved by the regmask \p RegMask.
@@ -114,8 +114,8 @@ class LiveRegUnits {
/// Returns true if no part of physical register \p Reg is live.
bool available(MCPhysReg Reg) const {
- for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
- if (Units.test(*Unit))
+ for (MCRegUnit Unit : TRI->regunits(Reg)) {
+ if (Units.test(Unit))
return false;
}
return true;
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index e6cc0333dc79c..62a955f6b7d43 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -428,8 +428,8 @@ class TargetRegisterInfo : public MCRegisterInfo {
/// Returns true if Reg contains RegUnit.
bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
- for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
- if (Register(*Units) == RegUnit)
+ for (MCRegUnit Unit : regunits(Reg))
+ if (Register(Unit) == RegUnit)
return true;
return false;
}
diff --git a/llvm/include/llvm/MC/MCRegister.h b/llvm/include/llvm/MC/MCRegister.h
index 1e2bdc32885fe..530c1870abd6a 100644
--- a/llvm/include/llvm/MC/MCRegister.h
+++ b/llvm/include/llvm/MC/MCRegister.h
@@ -20,6 +20,15 @@ namespace llvm {
/// but not necessarily virtual registers.
using MCPhysReg = uint16_t;
+/// Register units are used to compute register aliasing. Every register has at
+/// least one register unit, but it can have more. Two registers overlap if and
+/// only if they have a common register unit.
+///
+/// A target with a complicated sub-register structure will typically have many
+/// fewer register units than actual registers. MCRI::getNumRegUnits() returns
+/// the number of register units in the target.
+using MCRegUnit = unsigned;
+
/// Wrapper class representing physical registers. Should be passed by value.
class MCRegister {
friend hash_code hash_value(const MCRegister &);
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index be69037c3448b..ede01d6249246 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -27,6 +27,7 @@
namespace llvm {
+class MCRegUnitIterator;
class MCSubRegIterator;
class MCSuperRegIterator;
@@ -253,6 +254,9 @@ class MCRegisterInfo {
iterator_range<MCSuperRegIterator>>
sub_and_superregs_inclusive(MCRegister Reg) const;
+ /// Returns an iterator range over all regunits for \p Reg.
+ iterator_range<MCRegUnitIterator> regunits(MCRegister Reg) const;
+
// These iterators are allowed to sub-class DiffListIterator and access
// internal list pointers.
friend class MCSubRegIterator;
@@ -615,23 +619,19 @@ inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) co
// Register Units
//===----------------------------------------------------------------------===//
-// Register units are used to compute register aliasing. Every register has at
-// least one register unit, but it can have more. Two registers overlap if and
-// only if they have a common register unit.
-//
-// A target with a complicated sub-register structure will typically have many
-// fewer register units than actual registers. MCRI::getNumRegUnits() returns
-// the number of register units in the target.
-
// MCRegUnitIterator enumerates a list of register units for Reg. The list is
// in ascending numerical order.
-class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
+class MCRegUnitIterator
+ : public iterator_adaptor_base<MCRegUnitIterator,
+ MCRegisterInfo::DiffListIterator,
+ std::forward_iterator_tag, const MCRegUnit> {
// The value must be kept in sync with RegisterInfoEmitter.cpp.
static constexpr unsigned RegUnitBits = 12;
+ // Cache the current value, so that we can return a reference to it.
+ MCRegUnit Val;
public:
- /// MCRegUnitIterator - Create an iterator that traverses the register units
- /// in Reg.
+ /// Constructs an end iterator.
MCRegUnitIterator() = default;
MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) {
@@ -641,13 +641,20 @@ class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
unsigned RU = MCRI->get(Reg).RegUnits;
unsigned FirstRU = RU & ((1u << RegUnitBits) - 1);
unsigned Offset = RU >> RegUnitBits;
- init(FirstRU, MCRI->DiffLists + Offset);
+ I.init(FirstRU, MCRI->DiffLists + Offset);
+ Val = MCRegUnit(*I);
}
+ const MCRegUnit &operator*() const { return Val; }
+
+ using iterator_adaptor_base::operator++;
MCRegUnitIterator &operator++() {
- MCRegisterInfo::DiffListIterator::operator++();
+ Val = MCRegUnit(*++I);
return *this;
}
+
+ /// Returns true if this iterator is not yet at the end.
+ bool isValid() const { return I.isValid(); }
};
/// MCRegUnitMaskIterator enumerates a list of register units and their
@@ -810,6 +817,11 @@ MCRegisterInfo::sub_and_superregs_inclusive(MCRegister Reg) const {
return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg));
}
+inline iterator_range<MCRegUnitIterator>
+MCRegisterInfo::regunits(MCRegister Reg) const {
+ return make_range({Reg, this}, MCRegUnitIterator());
+}
+
} // end namespace llvm
#endif // LLVM_MC_MCREGISTERINFO_H
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index 50ce812eb9fac..b8502b455f587 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -709,8 +709,8 @@ static void interpretValues(const MachineInstr *CurMI,
for (auto &FwdReg : ForwardedRegWorklist)
if (TRI.regsOverlap(FwdReg.first, MO.getReg()))
Defs.insert(FwdReg.first);
- for (MCRegUnitIterator Units(MO.getReg(), &TRI); Units.isValid(); ++Units)
- NewClobberedRegUnits.insert(*Units);
+ for (MCRegUnit Unit : TRI.regunits(MO.getReg()))
+ NewClobberedRegUnits.insert(Unit);
}
}
};
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 9789381f7601a..618e41894b29b 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -124,9 +124,9 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
MCRegister OriginalReg = MO.getReg().asMCReg();
// Update only undef operands that have reg units that are mapped to one root.
- for (MCRegUnitIterator Unit(OriginalReg, TRI); Unit.isValid(); ++Unit) {
+ for (MCRegUnit Unit : TRI->regunits(OriginalReg)) {
unsigned NumRoots = 0;
- for (MCRegUnitRootIterator Root(*Unit, TRI); Root.isValid(); ++Root) {
+ for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
NumRoots++;
if (NumRoots > 1)
return false;
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index 30e26d40e2299..61867d74bfa29 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -263,9 +263,8 @@ bool SSAIfConv::InstrDependenciesAllowIfConv(MachineInstr *I) {
// Remember clobbered regunits.
if (MO.isDef() && Reg.isPhysical())
- for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
- ++Units)
- ClobberedRegUnits.set(*Units);
+ for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
+ ClobberedRegUnits.set(Unit);
if (!MO.readsReg() || !Reg.isVirtual())
continue;
@@ -394,19 +393,17 @@ bool SSAIfConv::findInsertionPoint() {
continue;
// I clobbers Reg, so it isn't live before I.
if (MO.isDef())
- for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
- ++Units)
- LiveRegUnits.erase(*Units);
+ for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
+ LiveRegUnits.erase(Unit);
// Unless I reads Reg.
if (MO.readsReg())
Reads.push_back(Reg.asMCReg());
}
// Anything read by I is live before I.
while (!Reads.empty())
- for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
- ++Units)
- if (ClobberedRegUnits.test(*Units))
- LiveRegUnits.insert(*Units);
+ for (MCRegUnit Unit : TRI->regunits(Reads.pop_back_val()))
+ if (ClobberedRegUnits.test(Unit))
+ LiveRegUnits.insert(Unit);
// We can't insert before a terminator.
if (I != FirstTerm && I->isTerminator())
diff --git a/llvm/lib/CodeGen/InterferenceCache.cpp b/llvm/lib/CodeGen/InterferenceCache.cpp
index 3cab9e5734ee3..ae197ee5553ae 100644
--- a/llvm/lib/CodeGen/InterferenceCache.cpp
+++ b/llvm/lib/CodeGen/InterferenceCache.cpp
@@ -93,8 +93,8 @@ void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
// Invalidate all iterators.
PrevPos = SlotIndex();
unsigned i = 0;
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
- RegUnits[i].VirtTag = LIUArray[*Units].getTag();
+ for (MCRegUnit Unit : TRI->regunits(PhysReg))
+ RegUnits[i++].VirtTag = LIUArray[Unit].getTag();
}
void InterferenceCache::Entry::reset(MCRegister physReg,
@@ -110,20 +110,21 @@ void InterferenceCache::Entry::reset(MCRegister physReg,
// Reset iterators.
PrevPos = SlotIndex();
RegUnits.clear();
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- RegUnits.push_back(LIUArray[*Units]);
- RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ RegUnits.push_back(LIUArray[Unit]);
+ RegUnits.back().Fixed = &LIS->getRegUnit(Unit);
}
}
bool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray,
const TargetRegisterInfo *TRI) {
unsigned i = 0, e = RegUnits.size();
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) {
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
if (i == e)
return false;
- if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag))
+ if (LIUArray[Unit].changedSince(RegUnits[i].VirtTag))
return false;
+ ++i;
}
return i == e;
}
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
index 110f30b507583..57df9b67fd026 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
@@ -2513,8 +2513,8 @@ void InstrRefBasedLDV::placeMLocPHIs(
Register R = MTracker->LocIdxToLocID[L];
SmallSet<Register, 8> FoundRegUnits;
bool AnyIllegal = false;
- for (MCRegUnitIterator RUI(R.asMCReg(), TRI); RUI.isValid(); ++RUI) {
- for (MCRegUnitRootIterator URoot(*RUI, TRI); URoot.isValid(); ++URoot){
+ for (MCRegUnit Unit : TRI->regunits(R.asMCReg())) {
+ for (MCRegUnitRootIterator URoot(Unit, TRI); URoot.isValid(); ++URoot) {
if (!MTracker->isRegisterTracked(*URoot)) {
// Not all roots were loaded into the tracking map: this register
// isn't actually def'd anywhere, we only read from it. Generate PHIs
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 36690ecec08a5..da55e7f7284b3 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -329,8 +329,7 @@ void LiveIntervals::computeLiveInRegUnits() {
SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);
LLVM_DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB));
for (const auto &LI : MBB.liveins()) {
- for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
- unsigned Unit = *Units;
+ for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
LiveRange *LR = RegUnitRanges[Unit];
if (!LR) {
// Use segment set to speed-up initial computation of the live range.
@@ -704,9 +703,8 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
// Find the regunit intervals for the assigned register. They may overlap
// the virtual register live range, cancelling any kills.
RU.clear();
- for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid();
- ++Unit) {
- const LiveRange &RURange = getRegUnit(*Unit);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ const LiveRange &RURange = getRegUnit(Unit);
if (RURange.empty())
continue;
RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
@@ -1052,10 +1050,9 @@ class LiveIntervals::HMEditor {
// For physregs, only update the regunits that actually have a
// precomputed live range.
- for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid();
- ++Units)
- if (LiveRange *LR = getRegUnitLI(*Units))
- updateRange(*LR, *Units, LaneBitmask::getNone());
+ for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
+ if (LiveRange *LR = getRegUnitLI(Unit))
+ updateRange(*LR, Unit, LaneBitmask::getNone());
}
if (hasRegMask)
updateRegMaskSlots();
@@ -1703,8 +1700,8 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
}
void LiveIntervals::removePhysRegDefAt(MCRegister Reg, SlotIndex Pos) {
- for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
- if (LiveRange *LR = getCachedRegUnit(*Unit))
+ for (MCRegUnit Unit : TRI->regunits(Reg)) {
+ if (LiveRange *LR = getCachedRegUnit(Unit))
if (VNInfo *VNI = LR->getVNInfoAt(Pos))
LR->removeValNo(VNI);
}
diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp
index 6ca7f00a78855..6df7e5c108628 100644
--- a/llvm/lib/CodeGen/LiveRegMatrix.cpp
+++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp
@@ -93,8 +93,8 @@ static bool foreachUnit(const TargetRegisterInfo *TRI,
}
}
} else {
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- if (Func(*Units, VRegInterval))
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ if (Func(Unit, VRegInterval))
return true;
}
}
@@ -136,8 +136,8 @@ void LiveRegMatrix::unassign(const LiveInterval &VirtReg) {
}
bool LiveRegMatrix::isPhysRegUsed(MCRegister PhysReg) const {
- for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
- if (!Matrix[*Unit].empty())
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ if (!Matrix[Unit].empty())
return true;
}
return false;
@@ -216,7 +216,7 @@ bool LiveRegMatrix::checkInterference(SlotIndex Start, SlotIndex End,
LR.addSegment(Seg);
// Check for interference with that segment
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
// LR is stack-allocated. LiveRegMatrix caches queries by a key that
// includes the address of the live range. If (for the same reg unit) this
// checkInterference overload is called twice, without any other query()
@@ -230,7 +230,7 @@ bool LiveRegMatrix::checkInterference(SlotIndex Start, SlotIndex End,
// subtle bugs due to query identity. Avoiding caching, for example, would
// greatly simplify things.
LiveIntervalUnion::Query Q;
- Q.reset(UserTag, LR, Matrix[*Units]);
+ Q.reset(UserTag, LR, Matrix[Unit]);
if (Q.checkInterference())
return true;
}
@@ -239,8 +239,8 @@ bool LiveRegMatrix::checkInterference(SlotIndex Start, SlotIndex End,
Register LiveRegMatrix::getOneVReg(unsigned PhysReg) const {
const LiveInterval *VRegInterval = nullptr;
- for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
- if ((VRegInterval = Matrix[*Unit].getOneVReg()))
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ if ((VRegInterval = Matrix[Unit].getOneVReg()))
return VRegInterval->reg();
}
diff --git a/llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp b/llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp
index 1ff4356b60461..e7d745c7c230c 100644
--- a/llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp
+++ b/llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp
@@ -611,8 +611,8 @@ bool MLEvictAdvisor::loadInterferenceFeatures(
unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg());
SmallVector<const LiveInterval *, MaxInterferences> InterferingIntervals;
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
// Different from the default heuristic, we don't make any assumptions
// about what having more than 10 results in the query may mean.
const auto &IFIntervals = Q.interferingVRegs(EvictInterferenceCutoff);
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 03eac55e39792..d443b895d1b81 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -121,8 +121,8 @@ class CopyTracker {
const TargetRegisterInfo &TRI) {
for (MCRegister Reg : Regs) {
// Source of copy is no longer available for propagation.
- for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) {
- auto CI = Copies.find(*RUI);
+ for (MCRegUnit Unit : TRI.regunits(Reg)) {
+ auto CI = Copies.find(Unit);
if (CI != Copies.end())
CI->second.Avail = false;
}
@@ -137,8 +137,8 @@ class CopyTracker {
// and invalidate all of them.
SmallSet<MCRegister, 8> RegsToInvalidate;
RegsToInvalidate.insert(Reg);
- for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) {
- auto I = Copies.find(*RUI);
+ for (MCRegUnit Unit : TRI.regunits(Reg)) {
+ auto I = Copies.find(Unit);
if (I != Copies.end()) {
if (MachineInstr *MI = I->second.MI) {
std::optional<DestSourcePair> CopyOperands =
@@ -154,15 +154,15 @@ class CopyTracker {
}
}
for (MCRegister InvalidReg : RegsToInvalidate)
- for (MCRegUnitIterator RUI(InvalidReg, &TRI); RUI.isValid(); ++RUI)
- Copies.erase(*RUI);
+ for (MCRegUnit Unit : TRI.regunits(InvalidReg))
+ Copies.erase(Unit);
}
/// Clobber a single register, removing it from the tracker's copy maps.
void clobberRegister(MCRegister Reg, const TargetRegisterInfo &TRI,
const TargetInstrInfo &TII, bool UseCopyInstr) {
- for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) {
- auto I = Copies.find(*RUI);
+ for (MCRegUnit Unit : TRI.regunits(Reg)) {
+ auto I = Copies.find(Unit);
if (I != Copies.end()) {
// When we clobber the source of a copy, we need to clobber everything
// it defined.
@@ -192,13 +192,13 @@ class CopyTracker {
MCRegister Def = CopyOperands->Destination->getReg().asMCReg();
// Remember Def is defined by the copy.
- for (MCRegUnitIterator RUI(Def, &TRI); RUI.isValid(); ++RUI)
- Copies[*RUI] = {MI, nullptr, {}, true};
+ for (MCRegUnit Unit : TRI.regunits(Def))
+ Copies[Unit] = {MI, nullptr, {}, true};
// Remember source that's copied to Def. Once it's clobbered, then
// it's no longer available for copy propagation.
- for (MCRegUnitIterator RUI(Src, &TRI); RUI.isValid(); ++RUI) {
- auto I = Copies.insert({*RUI, {nullptr, nullptr, {}, false}});
+ for (MCRegUnit Unit : TRI.regunits(Src)) {
+ auto I = Copies.insert({Unit, {nullptr, nullptr, {}, false}});
auto &Copy = I.first->second;
if (!is_contained(Copy.DefRegs, Def))
Copy.DefRegs.push_back(Def);
@@ -410,8 +410,8 @@ void MachineCopyPropagation::ReadRegister(MCRegister Reg, MachineInstr &Reader,
// If 'Reg' is defined by a copy, the copy is no longer a candidate
// for elimination. If a copy is "read" by a debug user, record the user
// for propagation.
- for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
- if (MachineInstr *Copy = Tracker.findCopyForUnit(*RUI, *TRI)) {
+ for (MCRegUnit Unit : TRI->regunits(Reg)) {
+ if (MachineInstr *Copy = Tracker.findCopyForUnit(Unit, *TRI)) {
if (DT == RegularUse) {
LLVM_DEBUG(dbgs() << "MCP: Copy is used - not dead: "; Copy->dump());
MaybeDeadCopies.remove(Copy);
@@ -1027,9 +1027,8 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
// Check if the register in the debug instruction is utilized
// in a copy instruction, so we can update the debug info if the
// register is changed.
- for (MCRegUnitIterator RUI(MO.getReg().asMCReg(), TRI); RUI.isValid();
- ++RUI) {
- if (auto *Copy = Tracker.findCopyDefViaUnit(*RUI, *TRI)) {
+ for (MCRegUnit Unit : TRI->regunits(MO.getReg().asMCReg())) {
+ if (auto *Copy = Tracker.findCopyDefViaUnit(Unit, *TRI)) {
CopyDbgUsers[Copy].insert(&MI);
}
}
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 3f9fbb7e20297..c7e7497dab368 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1562,9 +1562,8 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
if (Reg.isVirtual())
Uses.insert(Reg);
else if (MRI.isAllocatable(Reg))
- for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
- ++Units)
- Uses.insert(*Units);
+ for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
+ Uses.insert(Unit);
}
}
for (SUnit *SU : NS)
@@ -1576,11 +1575,10 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
LiveOutRegs.push_back(RegisterMaskPair(Reg,
LaneBitmask::getNone()));
} else if (MRI.isAllocatable(Reg)) {
- for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
- ++Units)
- if (!Uses.count(*Units))
- LiveOutRegs.push_back(RegisterMaskPair(*Units,
- LaneBitmask::getNone()));
+ for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
+ if (!Uses.count(Unit))
+ LiveOutRegs.push_back(
+ RegisterMaskPair(Unit, LaneBitmask::getNone()));
}
}
RPTracker.addLiveRegs(LiveOutRegs);
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index e18a19e785b04..72484dfc5ebc4 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -1785,9 +1785,8 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
}
// Record debug use of each reg unit.
- for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid();
- ++RI)
- MIUnits[*RI].push_back(MO.getReg());
+ for (MCRegUnit Unit : TRI->regunits(MO.getReg()))
+ MIUnits[Unit].push_back(MO.getReg());
}
}
if (IsValid) {
@@ -1837,8 +1836,8 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
// writes any of those units then the corresponding DBG_VALUEs must sink.
MapVector<MachineInstr *, MIRegs::second_type> DbgValsToSinkMap;
for (auto &MO : MI.all_defs()) {
- for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid(); ++RI) {
- for (const auto &MIRegs : SeenDbgInstrs.lookup(*RI)) {
+ for (MCRegUnit Unit : TRI->regunits(MO.getReg())) {
+ for (const auto &MIRegs : SeenDbgInstrs.lookup(Unit)) {
auto &Regs = DbgValsToSinkMap[MIRegs.first];
for (unsigned Reg : MIRegs.second)
Regs.push_back(Reg);
diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
index 2254c84c354c3..4f66f2e672d18 100644
--- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp
+++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
@@ -735,8 +735,8 @@ static void updatePhysDepsDownwards(const MachineInstr *UseMI,
// Identify dependencies.
if (!MO.readsReg())
continue;
- for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
- SparseSet<LiveRegUnit>::iterator I = RegUnits.find(*Units);
+ for (MCRegUnit Unit : TRI->regunits(Reg)) {
+ SparseSet<LiveRegUnit>::iterator I = RegUnits.find(Unit);
if (I == RegUnits.end())
continue;
Deps.push_back(DataDep(I->MI, I->Op, MO.getOperandNo()));
@@ -747,15 +747,14 @@ static void updatePhysDepsDownwards(const MachineInstr *UseMI,
// Update RegUnits to reflect live registers after UseMI.
// First kills.
for (MCRegister Kill : Kills)
- for (MCRegUnitIterator Units(Kill, TRI); Units.isValid(); ++Units)
- RegUnits.erase(*Units);
+ for (MCRegUnit Unit : TRI->regunits(Kill))
+ RegUnits.erase(Unit);
// Second, live defs.
for (unsigned DefOp : LiveDefOps) {
- for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg().asMCReg(),
- TRI);
- Units.isValid(); ++Units) {
- LiveRegUnit &LRU = RegUnits[*Units];
+ for (MCRegUnit Unit :
+ TRI->regunits(UseMI->getOperand(DefOp).getReg().asMCReg())) {
+ LiveRegUnit &LRU = RegUnits[Unit];
LRU.MI = UseMI;
LRU.Op = DefOp;
}
@@ -922,9 +921,8 @@ static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height,
continue;
// This is a def of Reg. Remove corresponding entries from RegUnits, and
// update MI Height to consider the physreg dependencies.
- for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
- ++Units) {
- SparseSet<LiveRegUnit>::iterator I = RegUnits.find(*Units);
+ for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) {
+ SparseSet<LiveRegUnit>::iterator I = RegUnits.find(Unit);
if (I == RegUnits.end())
continue;
unsigned DepHeight = I->Cycle;
@@ -943,8 +941,8 @@ static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height,
// Now we know the height of MI. Update any regunits read.
for (size_t I = 0, E = ReadOps.size(); I != E; ++I) {
MCRegister Reg = MI.getOperand(ReadOps[I]).getReg().asMCReg();
- for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
- LiveRegUnit &LRU = RegUnits[*Units];
+ for (MCRegUnit Unit : TRI->regunits(Reg)) {
+ LiveRegUnit &LRU = RegUnits[Unit];
// Set the height to the highest reader of the unit.
if (LRU.Cycle <= Height && LRU.MI != &MI) {
LRU.Cycle = Height;
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index f960869ec28b0..7acd3c4039e82 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2440,12 +2440,11 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
// Check the cached regunit intervals.
if (Reg.isPhysical() && !isReserved(Reg)) {
- for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
- ++Units) {
- if (MRI->isReservedRegUnit(*Units))
+ for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) {
+ if (MRI->isReservedRegUnit(Unit))
continue;
- if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
- checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
+ if (const LiveRange *LR = LiveInts->getCachedRegUnit(Unit))
+ checkLivenessAtUse(MO, MONum, UseIdx, *LR, Unit);
}
}
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index d69bf2f784d4e..caf4f61d027db 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1287,8 +1287,8 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
MCRegister Reg = MO.getReg();
// This picks up sibling registers (e.q. %al -> %ah).
- for (MCRegUnitIterator Unit(Reg, &TRI); Unit.isValid(); ++Unit)
- RegsToZero.reset(*Unit);
+ for (MCRegUnit Unit : TRI.regunits(Reg))
+ RegsToZero.reset(Unit);
for (MCPhysReg SReg : TRI.sub_and_superregs_inclusive(Reg))
RegsToZero.reset(SReg);
diff --git a/llvm/lib/CodeGen/RDFRegisters.cpp b/llvm/lib/CodeGen/RDFRegisters.cpp
index 341a79b8717b1..8f2a12ac20b08 100644
--- a/llvm/lib/CodeGen/RDFRegisters.cpp
+++ b/llvm/lib/CodeGen/RDFRegisters.cpp
@@ -88,8 +88,8 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
for (unsigned I = 1, E = TRI.getNumRegs(); I != E; ++I) {
if (!(MB[I / 32] & (1u << (I % 32))))
continue;
- for (MCRegUnitIterator U(MCRegister::from(I), &TRI); U.isValid(); ++U)
- PU.set(*U);
+ for (MCRegUnit Unit : TRI.regunits(MCRegister::from(I)))
+ PU.set(Unit);
}
MaskInfos[M].Units = PU.flip();
}
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
index d9ced9191fae9..75fbc8ba35b16 100644
--- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -65,13 +65,13 @@ void ReachingDefAnalysis::enterBasicBlock(MachineBasicBlock *MBB) {
// This is the entry block.
if (MBB->pred_empty()) {
for (const auto &LI : MBB->liveins()) {
- for (MCRegUnitIterator Unit(LI.PhysReg, TRI); Unit.isValid(); ++Unit) {
+ for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
// Treat function live-ins as if they were defined just before the first
// instruction. Usually, function arguments are set up immediately
// before the call.
- if (LiveRegs[*Unit] != -1) {
- LiveRegs[*Unit] = -1;
- MBBReachingDefs[MBBNumber][*Unit].push_back(-1);
+ if (LiveRegs[Unit] != -1) {
+ LiveRegs[Unit] = -1;
+ MBBReachingDefs[MBBNumber][Unit].push_back(-1);
}
}
}
@@ -128,16 +128,15 @@ void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
for (auto &MO : MI->operands()) {
if (!isValidRegDef(MO))
continue;
- for (MCRegUnitIterator Unit(MO.getReg().asMCReg(), TRI); Unit.isValid();
- ++Unit) {
+ for (MCRegUnit Unit : TRI->regunits(MO.getReg().asMCReg())) {
// This instruction explicitly defines the current reg unit.
- LLVM_DEBUG(dbgs() << printRegUnit(*Unit, TRI) << ":\t" << CurInstr
- << '\t' << *MI);
+ LLVM_DEBUG(dbgs() << printRegUnit(Unit, TRI) << ":\t" << CurInstr << '\t'
+ << *MI);
// How many instructions since this reg unit was last written?
- if (LiveRegs[*Unit] != CurInstr) {
- LiveRegs[*Unit] = CurInstr;
- MBBReachingDefs[MBBNumber][*Unit].push_back(CurInstr);
+ if (LiveRegs[Unit] != CurInstr) {
+ LiveRegs[Unit] = CurInstr;
+ MBBReachingDefs[MBBNumber][Unit].push_back(CurInstr);
}
}
}
@@ -269,8 +268,8 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI,
assert(MBBNumber < MBBReachingDefs.size() &&
"Unexpected basic block number.");
int LatestDef = ReachingDefDefaultVal;
- for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
- for (int Def : MBBReachingDefs[MBBNumber][*Unit]) {
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ for (int Def : MBBReachingDefs[MBBNumber][Unit]) {
if (Def >= InstId)
break;
DefRes = Def;
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index bef95e235b16b..6661991396302 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -213,8 +213,8 @@ bool RABasic::spillInterferences(const LiveInterval &VirtReg,
SmallVector<const LiveInterval *, 8> Intfs;
// Collect interferences assigned to any alias of the physical register.
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
for (const auto *Intf : reverse(Q.interferingVRegs())) {
if (!Intf->isSpillable() || Intf->weight() > VirtReg.weight())
return false;
diff --git a/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp b/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
index daba130bf1583..81f3d2c8099f1 100644
--- a/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
+++ b/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
@@ -201,8 +201,8 @@ bool DefaultEvictionAdvisor::canEvictInterferenceBasedOnCost(
unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg());
EvictionCost Cost;
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
// If there is 10 or more interferences, chances are one is heavier.
const auto &Interferences = Q.interferingVRegs(EvictInterferenceCutoff);
if (Interferences.size() >= EvictInterferenceCutoff)
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index 40d2e968f46f2..d9029f070a3b4 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -161,8 +161,8 @@ namespace {
/// Mark a physreg as used in this instruction.
void markRegUsedInInstr(MCPhysReg PhysReg) {
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
- UsedInInstr.insert(*Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg))
+ UsedInInstr.insert(Unit);
}
// Check if physreg is clobbered by instruction's regmask(s).
@@ -176,10 +176,10 @@ namespace {
bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const {
if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
return true;
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- if (UsedInInstr.count(*Units))
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ if (UsedInInstr.count(Unit))
return true;
- if (LookAtPhysRegUses && PhysRegUses.count(*Units))
+ if (LookAtPhysRegUses && PhysRegUses.count(Unit))
return true;
}
return false;
@@ -188,14 +188,14 @@ namespace {
/// Mark physical register as being used in a register use operand.
/// This is only used by the special livethrough handling code.
void markPhysRegUsedInInstr(MCPhysReg PhysReg) {
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
- PhysRegUses.insert(*Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg))
+ PhysRegUses.insert(Unit);
}
/// Remove mark of physical register being used in the instruction.
void unmarkRegUsedInInstr(MCPhysReg PhysReg) {
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
- UsedInInstr.erase(*Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg))
+ UsedInInstr.erase(Unit);
}
enum : unsigned {
@@ -310,13 +310,13 @@ bool RegAllocFast::shouldAllocateRegister(const Register Reg) const {
}
void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) {
- for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI)
- RegUnitStates[*UI] = NewState;
+ for (MCRegUnit Unit : TRI->regunits(PhysReg))
+ RegUnitStates[Unit] = NewState;
}
bool RegAllocFast::isPhysRegFree(MCPhysReg PhysReg) const {
- for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) {
- if (RegUnitStates[*UI] != regFree)
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ if (RegUnitStates[Unit] != regFree)
return false;
}
return true;
@@ -595,8 +595,7 @@ bool RegAllocFast::definePhysReg(MachineInstr &MI, MCPhysReg Reg) {
bool RegAllocFast::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) {
bool displacedAny = false;
- for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) {
- unsigned Unit = *UI;
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
switch (unsigned VirtReg = RegUnitStates[Unit]) {
default: {
LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
@@ -650,8 +649,8 @@ void RegAllocFast::freePhysReg(MCPhysReg PhysReg) {
/// disabled - it can be allocated directly.
/// \returns spillImpossible when PhysReg or an alias can't be spilled.
unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const {
- for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) {
- switch (unsigned VirtReg = RegUnitStates[*UI]) {
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ switch (unsigned VirtReg = RegUnitStates[Unit]) {
case regFree:
break;
case regPreAssigned:
@@ -1115,8 +1114,8 @@ void RegAllocFast::dumpState() const {
if (PhysReg != 0) {
assert(Register::isPhysicalRegister(PhysReg) &&
"mapped to physreg");
- for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) {
- assert(RegUnitStates[*UI] == VirtReg && "inverse map valid");
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ assert(RegUnitStates[Unit] == VirtReg && "inverse map valid");
}
}
}
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index a9c85e558bd3c..57cddd08b1b06 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -487,8 +487,8 @@ void RAGreedy::evictInterference(const LiveInterval &VirtReg,
// Collect all interfering virtregs first.
SmallVector<const LiveInterval *, 8> Intfs;
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
// We usually have the interfering VRegs cached so collectInterferingVRegs()
// should be fast, we may need to recalculate if when
diff erent physregs
// overlap the same register unit so we had
diff erent SubRanges queried
@@ -1404,9 +1404,9 @@ void RAGreedy::calcGapWeights(MCRegister PhysReg,
GapWeight.assign(NumGaps, 0.0f);
// Add interference from each overlapping register.
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
- .checkInterference())
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ if (!Matrix->query(const_cast<LiveInterval &>(SA->getParent()), Unit)
+ .checkInterference())
continue;
// We know that VirtReg is a continuous interval from FirstInstr to
@@ -1417,7 +1417,7 @@ void RAGreedy::calcGapWeights(MCRegister PhysReg,
// StartIdx and after StopIdx.
//
LiveIntervalUnion::SegmentIter IntI =
- Matrix->getLiveUnions()[*Units] .find(StartIdx);
+ Matrix->getLiveUnions()[Unit].find(StartIdx);
for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
// Skip the gaps before IntI.
while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
@@ -1439,8 +1439,8 @@ void RAGreedy::calcGapWeights(MCRegister PhysReg,
}
// Add fixed interference.
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- const LiveRange &LR = LIS->getRegUnit(*Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ const LiveRange &LR = LIS->getRegUnit(Unit);
LiveRange::const_iterator I = LR.find(StartIdx);
LiveRange::const_iterator E = LR.end();
@@ -1771,8 +1771,8 @@ bool RAGreedy::mayRecolorAllInterferences(
SmallLISet &RecoloringCandidates, const SmallVirtRegSet &FixedRegisters) {
const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg());
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
// If there is LastChanceRecoloringMaxInterference or more interferences,
// chances are one would not be recolorable.
if (Q.interferingVRegs(LastChanceRecoloringMaxInterference).size() >=
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index b3d926eeb5523..925a0f085c4bc 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -634,8 +634,8 @@ void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
// vregLI overlaps fixed regunit interference.
bool Interference = false;
- for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
- if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
+ for (MCRegUnit Unit : TRI.regunits(PReg)) {
+ if (VRegLI.overlaps(LIS.getRegUnit(Unit))) {
Interference = true;
break;
}
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 68827d0ea5e60..4fc1d3ebc8d93 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1539,9 +1539,8 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
// no live-ranges would have been created for ECX.
// Fix that!
SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
- for (MCRegUnitIterator Units(NewMI.getOperand(0).getReg(), TRI);
- Units.isValid(); ++Units)
- if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
+ for (MCRegUnit Unit : TRI->regunits(NewMI.getOperand(0).getReg()))
+ if (LiveRange *LR = LIS->getCachedRegUnit(Unit))
LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
}
@@ -1555,8 +1554,8 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
MCRegister Reg = NewMIImplDefs[i];
- for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
- if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ if (LiveRange *LR = LIS->getCachedRegUnit(Unit))
LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
}
@@ -2158,14 +2157,14 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
// Deny any overlapping intervals. This depends on all the reserved
// register live ranges to look like dead defs.
if (!MRI->isConstantPhysReg(DstReg)) {
- for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
+ for (MCRegUnit Unit : TRI->regunits(DstReg)) {
// Abort if not all the regunits are reserved.
- for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
+ for (MCRegUnitRootIterator RI(Unit, TRI); RI.isValid(); ++RI) {
if (!MRI->isReserved(*RI))
return false;
}
- if (RHS.overlaps(LIS->getRegUnit(*UI))) {
- LLVM_DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI)
+ if (RHS.overlaps(LIS->getRegUnit(Unit))) {
+ LLVM_DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(Unit, TRI)
<< '\n');
return false;
}
@@ -2244,8 +2243,8 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
deleteInstr(CopyMI);
// Create a new dead def at the new def location.
- for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
- LiveRange &LR = LIS->getRegUnit(*UI);
+ for (MCRegUnit Unit : TRI->regunits(DstReg)) {
+ LiveRange &LR = LIS->getRegUnit(Unit);
LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator());
}
}
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index d4c29f96a4f96..f86aa3a167202 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -521,9 +521,8 @@ class RegisterOperandsCollector {
if (Reg.isVirtual()) {
addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneBitmask::getAll()));
} else if (MRI.isAllocatable(Reg)) {
- for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid();
- ++Units)
- addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll()));
+ for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
+ addRegLanes(RegUnits, RegisterMaskPair(Unit, LaneBitmask::getAll()));
}
}
@@ -557,9 +556,8 @@ class RegisterOperandsCollector {
: MRI.getMaxLaneMaskForVReg(Reg);
addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneMask));
} else if (MRI.isAllocatable(Reg)) {
- for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid();
- ++Units)
- addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll()));
+ for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
+ addRegLanes(RegUnits, RegisterMaskPair(Unit, LaneBitmask::getAll()));
}
}
};
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index 22fce544ac2cc..c00d3fde64263 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -96,13 +96,13 @@ void RegScavenger::enterBasicBlockEnd(MachineBasicBlock &MBB) {
}
void RegScavenger::addRegUnits(BitVector &BV, MCRegister Reg) {
- for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
- BV.set(*RUI);
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ BV.set(Unit);
}
void RegScavenger::removeRegUnits(BitVector &BV, MCRegister Reg) {
- for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
- BV.reset(*RUI);
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ BV.reset(Unit);
}
void RegScavenger::determineKillsAndDefs() {
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 7faf5f52249e3..c3ea76bf8cea6 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1532,8 +1532,8 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
S.addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));
}
} else {
- for (MCRegUnitIterator Unit(RegA, TRI); Unit.isValid(); ++Unit) {
- if (LiveRange *LR = LIS->getCachedRegUnit(*Unit)) {
+ for (MCRegUnit Unit : TRI->regunits(RegA)) {
+ if (LiveRange *LR = LIS->getCachedRegUnit(Unit)) {
VNInfo *VNI =
LR->getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
LR->addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 8021ca1eb2f13..a816bd5b52dec 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -514,8 +514,8 @@ bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
SlotIndex MIIndex = LIS->getInstructionIndex(MI);
SlotIndex BeforeMIUses = MIIndex.getBaseIndex();
SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex();
- for (MCRegUnitIterator Unit(SuperPhysReg, TRI); Unit.isValid(); ++Unit) {
- const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
+ for (MCRegUnit Unit : TRI->regunits(SuperPhysReg)) {
+ const LiveRange &UnitRange = LIS->getRegUnit(Unit);
// If the regunit is live both before and after MI,
// we assume it is live through.
// Generally speaking, this is not true, because something like
@@ -633,9 +633,8 @@ void VirtRegRewriter::rewrite() {
// Don't bother maintaining accurate LiveIntervals for registers which were
// already allocated.
for (Register PhysReg : RewriteRegs) {
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid();
- ++Units) {
- LIS->removeRegUnit(*Units);
+ for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+ LIS->removeRegUnit(Unit);
}
}
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
index a3a13062a1e11..27036eb02153e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
@@ -368,11 +368,11 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {
// ignore this operand.
if (MI.getOpcode() == AMDGPU::V_WRITELANE_B32 && Op.isTied())
continue;
- for (MCRegUnitIterator UI(Op.getReg(), TRI); UI.isValid(); ++UI) {
- auto It = State.find(*UI);
+ for (MCRegUnit Unit : TRI->regunits(Op.getReg())) {
+ auto It = State.find(Unit);
if (It != State.end()) {
Delay.merge(It->second);
- State.erase(*UI);
+ State.erase(Unit);
}
}
}
@@ -389,8 +389,8 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {
for (const auto &Op : MI.defs()) {
unsigned Latency = SchedModel.computeOperandLatency(
&MI, Op.getOperandNo(), nullptr, 0);
- for (MCRegUnitIterator UI(Op.getReg(), TRI); UI.isValid(); ++UI)
- State[*UI] = DelayInfo(Type, Latency);
+ for (MCRegUnit Unit : TRI->regunits(Op.getReg()))
+ State[Unit] = DelayInfo(Type, Latency);
}
}
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index e03c5b5a59edd..dce3ac90c3b26 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -588,8 +588,8 @@ int GCNHazardRecognizer::getWaitStatesSinceSetReg(IsHazardFn IsHazard,
static void addRegUnits(const SIRegisterInfo &TRI, BitVector &BV,
MCRegister Reg) {
- for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI)
- BV.set(*RUI);
+ for (MCRegUnit Unit : TRI.regunits(Reg))
+ BV.set(Unit);
}
static void addRegsToSet(const SIRegisterInfo &TRI,
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
index db4bc2de25ee0..d2a5eb89da129 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -96,8 +96,8 @@ static bool isDefBetween(const SIRegisterInfo &TRI,
if (Reg.isVirtual())
return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx);
- for (MCRegUnitIterator UI(Reg.asMCReg(), &TRI); UI.isValid(); ++UI) {
- if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx))
+ for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg())) {
+ if (isDefBetween(LIS->getRegUnit(Unit), AndIdx, SelIdx))
return true;
}
@@ -320,8 +320,8 @@ bool SIOptimizeExecMaskingPreRA::optimizeElseBranch(MachineBasicBlock &MBB) {
// Instead just check that the def segments are adjacent.
SlotIndex StartIdx = LIS->getInstructionIndex(SaveExecMI);
SlotIndex EndIdx = LIS->getInstructionIndex(*AndExecMI);
- for (MCRegUnitIterator UI(ExecReg, TRI); UI.isValid(); ++UI) {
- LiveRange &RegUnit = LIS->getRegUnit(*UI);
+ for (MCRegUnit Unit : TRI->regunits(ExecReg)) {
+ LiveRange &RegUnit = LIS->getRegUnit(Unit);
if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx)))
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp b/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
index 8553a0ab2a685..8464cb3d6fc43 100644
--- a/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
@@ -101,8 +101,8 @@ void SIPostRABundler::collectUsedRegUnits(const MachineInstr &MI,
assert(!Op.getSubReg() &&
"subregister indexes should not be present after RA");
- for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
- UsedRegUnits.set(*Units);
+ for (MCRegUnit Unit : TRI->regunits(Reg))
+ UsedRegUnits.set(Unit);
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 996a02241326f..ce4c0ac95c575 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3110,9 +3110,8 @@ MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg,
DefIdx = V->def;
} else {
// Find last def.
- for (MCRegUnitIterator Units(Reg.asMCReg(), this); Units.isValid();
- ++Units) {
- LiveRange &LR = LIS->getRegUnit(*Units);
+ for (MCRegUnit Unit : regunits(Reg.asMCReg())) {
+ LiveRange &LR = LIS->getRegUnit(Unit);
if (VNInfo *V = LR.getVNInfoAt(UseIdx)) {
if (!DefIdx.isValid() ||
MDT.dominates(LIS->getInstructionFromIndex(DefIdx),
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index c93b2382e2f3c..92099605d04c3 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -454,14 +454,13 @@ void SIWholeQuadMode::markOperand(const MachineInstr &MI,
// Handle physical registers that we need to track; this is mostly relevant
// for VCC, which can appear as the (implicit) input of a uniform branch,
// e.g. when a loop counter is stored in a VGPR.
- for (MCRegUnitIterator RegUnit(Reg.asMCReg(), TRI); RegUnit.isValid();
- ++RegUnit) {
- LiveRange &LR = LIS->getRegUnit(*RegUnit);
+ for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) {
+ LiveRange &LR = LIS->getRegUnit(Unit);
const VNInfo *Value = LR.Query(LIS->getInstructionIndex(MI)).valueIn();
if (!Value)
continue;
- markDefs(MI, LR, *RegUnit, AMDGPU::NoSubRegister, Flag, Worklist);
+ markDefs(MI, LR, Unit, AMDGPU::NoSubRegister, Flag, Worklist);
}
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
index 837812ab85c41..0d8c71f9f2e69 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
@@ -314,10 +314,7 @@ namespace {
// copy to be removed, or somewhere in between there and here). This
// is necessary only if it is a physical register.
if (!AddendSrcReg.isVirtual())
- for (MCRegUnitIterator Units(AddendSrcReg.asMCReg(), TRI);
- Units.isValid(); ++Units) {
- unsigned Unit = *Units;
-
+ for (MCRegUnit Unit : TRI->regunits(AddendSrcReg.asMCReg())) {
LiveRange &AddendSrcRange = LIS->getRegUnit(Unit);
AddendSrcRange.extendInBlock(LIS->getMBBStartIdx(&MBB),
FMAIdx.getRegSlot());
diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp
index c2d6b7660c892..09578913bff97 100644
--- a/llvm/unittests/MI/LiveIntervalTest.cpp
+++ b/llvm/unittests/MI/LiveIntervalTest.cpp
@@ -180,8 +180,8 @@ static bool checkRegUnitInterference(LiveIntervals &LIS,
return false;
CoalescerPair CP(VirtReg.reg(), PhysReg, TRI);
- for (MCRegUnitIterator Units(PhysReg, &TRI); Units.isValid(); ++Units) {
- const LiveRange &UnitRange = LIS.getRegUnit(*Units);
+ for (MCRegUnit Unit : TRI.regunits(PhysReg)) {
+ const LiveRange &UnitRange = LIS.getRegUnit(Unit);
if (VirtReg.overlaps(UnitRange, CP, *LIS.getSlotIndexes()))
return true;
}
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