[llvm] eb35786 - [ARM] Fix for invalid register in ReplaceConstByVPNOTs
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 15 12:46:25 PDT 2023
Author: David Green
Date: 2023-06-15T20:46:20+01:00
New Revision: eb35786fa274ab463996aa31c05bacd49a33315f
URL: https://github.com/llvm/llvm-project/commit/eb35786fa274ab463996aa31c05bacd49a33315f
DIFF: https://github.com/llvm/llvm-project/commit/eb35786fa274ab463996aa31c05bacd49a33315f.diff
LOG: [ARM] Fix for invalid register in ReplaceConstByVPNOTs
This ensures a removed register does not get reused as we replace constant vpt
values.
Added:
llvm/test/CodeGen/Thumb2/mve-pred-constfold.mir
Modified:
llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
index 6bad9d61238e7..5c113ccfdc157 100644
--- a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
+++ b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
@@ -913,7 +913,7 @@ bool MVETPAndVPTOptimisations::ReplaceVCMPsByVPNOTs(MachineBasicBlock &MBB) {
}
bool MVETPAndVPTOptimisations::ReplaceConstByVPNOTs(MachineBasicBlock &MBB,
- MachineDominatorTree *DT) {
+ MachineDominatorTree *DT) {
// Scan through the block, looking for instructions that use constants moves
// into VPR that are the negative of one another. These are expected to be
// COPY's to VCCRRegClass, from a t2MOVi or t2MOVi16. The last seen constant
@@ -965,6 +965,7 @@ bool MVETPAndVPTOptimisations::ReplaceConstByVPNOTs(MachineBasicBlock &MBB,
DeadInstructions.insert(MRI->getVRegDef(GPR));
}
LLVM_DEBUG(dbgs() << "Reusing predicate: in " << Instr);
+ VPR = LastVPTReg;
} else if (LastVPTReg != 0 && LastVPTImm == NotImm) {
// We have found the not of a previous constant. Create a VPNot of the
// earlier predicate reg and use it instead of the copy.
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-constfold.mir b/llvm/test/CodeGen/Thumb2/mve-pred-constfold.mir
new file mode 100644
index 0000000000000..31eef0fe8d34f
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-constfold.mir
@@ -0,0 +1,94 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - -verify-machineinstrs | FileCheck %s
+
+--- |
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv8.1m.main-none-unknown-eabi"
+
+ define arm_aapcs_vfpcc void @reg(<8 x i16> %acc0, <8 x i16> %acc1, ptr nocapture %px, i16 signext %p0) #0 {
+ entry:
+ %0 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 13107)
+ %1 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %0)
+ %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 52428)
+ %3 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %2)
+ %4 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %0)
+ %5 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc1, i32 0, <8 x i1> %2)
+ store i32 %1, ptr %px, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %px, i32 1
+ store i32 %3, ptr %arrayidx1, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %px, i32 2
+ store i32 %4, ptr %arrayidx2, align 4
+ %arrayidx3 = getelementptr inbounds i32, ptr %px, i32 3
+ store i32 %5, ptr %arrayidx3, align 4
+ ret void
+ }
+
+ declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1
+ declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
+ declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1
+
+ attributes #0 = { "target-features"="+mve" }
+
+...
+---
+name: reg
+alignment: 2
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: mqpr, preferred-register: '' }
+ - { id: 1, class: mqpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: rgpr, preferred-register: '' }
+ - { id: 5, class: vccr, preferred-register: '' }
+ - { id: 6, class: tgpreven, preferred-register: '' }
+ - { id: 7, class: rgpr, preferred-register: '' }
+ - { id: 8, class: vccr, preferred-register: '' }
+ - { id: 9, class: tgpreven, preferred-register: '' }
+ - { id: 10, class: tgpreven, preferred-register: '' }
+ - { id: 11, class: tgpreven, preferred-register: '' }
+liveins:
+ - { reg: '$q0', virtual-reg: '%0' }
+ - { reg: '$q1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%2' }
+body: |
+ bb.0.entry:
+ liveins: $q0, $q1, $r0
+
+ ; CHECK-LABEL: name: reg
+ ; CHECK: liveins: $q0, $q1, $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:mqpr = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:mqpr = COPY $q0
+ ; CHECK-NEXT: [[t2MOVi16_:%[0-9]+]]:rgpr = t2MOVi16 52428, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vccr = COPY [[t2MOVi16_]]
+ ; CHECK-NEXT: [[MVE_VADDVs16no_acc:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY2]], 1, [[COPY3]], $noreg
+ ; CHECK-NEXT: [[t2MOVi16_1:%[0-9]+]]:rgpr = t2MOVi16 13107, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vccr = COPY [[t2MOVi16_1]]
+ ; CHECK-NEXT: [[MVE_VADDVs16no_acc1:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY2]], 1, [[COPY4]], $noreg
+ ; CHECK-NEXT: [[MVE_VADDVs16no_acc2:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY1]], 1, [[COPY4]], $noreg
+ ; CHECK-NEXT: [[MVE_VADDVs16no_acc3:%[0-9]+]]:tgpreven = MVE_VADDVs16no_acc [[COPY1]], 1, [[COPY3]], $noreg
+ ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.px)
+ ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc]], [[COPY]], 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx1)
+ ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc2]], [[COPY]], 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx2)
+ ; CHECK-NEXT: t2STRi12 killed [[MVE_VADDVs16no_acc3]], [[COPY]], 12, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx3)
+ ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg
+ %2:gpr = COPY $r0
+ %1:mqpr = COPY $q1
+ %0:mqpr = COPY $q0
+ %4:rgpr = t2MOVi16 52428, 14 /* CC::al */, $noreg
+ %5:vccr = COPY %4
+ %6:tgpreven = MVE_VADDVs16no_acc %0, 1, %5, $noreg
+ t2STRi12 killed %6, %2, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx1)
+ %7:rgpr = t2MOVi16 13107, 14 /* CC::al */, $noreg
+ %8:vccr = COPY %7
+ %9:tgpreven = MVE_VADDVs16no_acc %0, 1, %8, $noreg
+ t2STRi12 killed %9, %2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.px)
+ %10:tgpreven = MVE_VADDVs16no_acc %1, 1, %8, $noreg
+ t2STRi12 killed %10, %2, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx2)
+ %11:tgpreven = MVE_VADDVs16no_acc %1, 1, %5, $noreg
+ t2STRi12 killed %11, %2, 12, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx3)
+ tBX_RET 14 /* CC::al */, $noreg
+
+...
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