[llvm] 7163539 - [DAGCombiner] When combining (sext_inreg (zext X), VT) -> (sext X) don't pass along the sext_inreg VT.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-06-15T11:47:42-07:00
New Revision: 7163539466d7e8930416e55dd9fd29891f8239f2

URL: https://github.com/llvm/llvm-project/commit/7163539466d7e8930416e55dd9fd29891f8239f2
DIFF: https://github.com/llvm/llvm-project/commit/7163539466d7e8930416e55dd9fd29891f8239f2.diff

LOG: [DAGCombiner] When combining (sext_inreg (zext X), VT) -> (sext X) don't pass along the sext_inreg VT.

ISD::SIGN_EXTEND is only supposed to have one operand, but we
were creating it with 2 operands.

Since we basically never check for extra operands this went
unnoticed.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 815c94b07a330..454944419293c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -14076,7 +14076,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
     SDValue N00 = N0.getOperand(0);
     if (N00.getScalarValueSizeInBits() == ExtVTBits &&
         (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
-      return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
+      return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00);
   }
 
   // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.