[PATCH] D153057: [RISCV] Introduce RISCVISD::VWMACC(U/SU)_VL opcode
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 15 11:22:14 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12379
+ return V;
+ else
+ return combineToVWMACC(N, DAG, Subtarget);
----------------
No `else` after `return`
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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:290
+ // Widening ternary operations with a mask as the fourth operand and VL as the
+ // fourth operand.
+ VWMACC_VL,
----------------
fourth -> fifth
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:404
+def riscv_vwmaccu_vl : SDNode<"RISCVISD::VWMACCU_VL", SDT_RISCVVWIntTernOp_VL, [SDNPCommutative]>;
+def riscv_vwmaccsu_vl : SDNode<"RISCVISD::VWMACCSU_VL", SDT_RISCVVWIntTernOp_VL, [SDNPCommutative]>;
+
----------------
riscv_vwmaccsu_vl isn't commutative
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1873
+defm : VPatWidenMultiplyAddVL_VV_VX2<riscv_vwmaccsu_vl, "PseudoVWMACCSU">;
defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmulsu_vl_oneuse, "PseudoVWMACCSU">;
foreach vtiTowti = AllWidenableIntVectors in {
----------------
Shoudln't the VPatWidenMultiplyAddVL_VV_VX be deleted?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D153057/new/
https://reviews.llvm.org/D153057
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