[PATCH] D153049: [AArch64] Try to convert vector shift operation into vector add operation

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 created this revision.
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It has been reported that the vector shift instructions tend to be worse than ADD/SUB on AArch64 cores.
This patch supports tablegen patterns for below simple transformation.

  x << 1  ==>  x + x


https://reviews.llvm.org/D153049

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
  llvm/test/CodeGen/AArch64/arm64-vshift.ll
  llvm/test/CodeGen/AArch64/rax1.ll
  llvm/test/CodeGen/AArch64/shl-to-add.ll
  llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/vector_splat-const-shift-of-constmasked.ll

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