[PATCH] D152963: [RISCV] Don't assume tail undefined if there's no policy op

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll:36
 ; CHECK-NEXT:    flh fa5, %lo(.LCPI1_0)(a1)
+; CHECK-NEXT:    vmset.m v0
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
----------------
https://reviews.llvm.org/D135122 is the reason why the RISCVISD::SETCC_VL nodes have the mask as both the passthru and mask operand. 
Do we still need to set v0 here to be correct?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152963/new/

https://reviews.llvm.org/D152963