[PATCH] D153011: [RISCV] Add TU variants to VPseudoBinaryM. NFC

Luke Lau via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 15 04:23:23 PDT 2023


luke created this revision.
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The aim is to use these in https://reviews.llvm.org/D152963 so that we
can preserve the passthru operand whilst also emitting the unmasked
variant. Like the mask variant, they are marked with forceTailAgnostic.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153011

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1897,10 +1897,13 @@
   let VLMul = MInfo.value in {
     def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
                                              Constraint>;
-    let ForceTailAgnostic = true in
-    def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
-                                                         Op2Class, Constraint>,
-                                   RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false>;
+    let ForceTailAgnostic = true in {
+      def "_" # MInfo.MX # "_TU" : VPseudoBinaryNoMaskTU<RetClass, Op1Class,
+                                                         Op2Class, Constraint>;
+      def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
+                                                           Op2Class, Constraint>,
+                                     RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+    }
   }
 }
 


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