[llvm] e95457d - [AMDGPU][AsmParser][NFC] Simplify v_interp-related operand definitions.
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 15 03:10:55 PDT 2023
Author: Ivan Kosarev
Date: 2023-06-15T11:04:56+01:00
New Revision: e95457d25b8ddeca67f2451598d1dd1b417d055d
URL: https://github.com/llvm/llvm-project/commit/e95457d25b8ddeca67f2451598d1dd1b417d055d
DIFF: https://github.com/llvm/llvm-project/commit/e95457d25b8ddeca67f2451598d1dd1b417d055d.diff
LOG: [AMDGPU][AsmParser][NFC] Simplify v_interp-related operand definitions.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D152897
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/LDSDIRInstructions.td
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/VOP3Instructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index e8a725b656607..5023e5394b86e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -150,7 +150,7 @@ class CustomOperandProps<bit optional = 0, string name = NAME> {
class CustomOperand<ValueType type, bit optional = 0, string name = NAME>
: Operand<type>, CustomOperandProps<optional, name>;
-class ImmOperand<ValueType type, string name, bit optional = 0,
+class ImmOperand<ValueType type, string name = NAME, bit optional = 0,
string printer = "print"#name>
: CustomOperand<type, optional, name> {
let ImmTy = "ImmTyNone";
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 91413945add8c..168beba6bfd89 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -146,7 +146,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
ImmTySendMsg,
ImmTyInterpSlot,
ImmTyInterpAttr,
- ImmTyAttrChan,
+ ImmTyInterpAttrChan,
ImmTyOpSel,
ImmTyOpSelHi,
ImmTyNegLo,
@@ -392,7 +392,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSDWADstUnused() const { return isImmTy(ImmTySDWADstUnused); }
bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }
bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }
- bool isAttrChan() const { return isImmTy(ImmTyAttrChan); }
+ bool isInterpAttrChan() const { return isImmTy(ImmTyInterpAttrChan); }
bool isOpSel() const { return isImmTy(ImmTyOpSel); }
bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
bool isNegLo() const { return isImmTy(ImmTyNegLo); }
@@ -1068,7 +1068,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
case ImmTySendMsg: OS << "SendMsg"; break;
case ImmTyInterpSlot: OS << "InterpSlot"; break;
case ImmTyInterpAttr: OS << "InterpAttr"; break;
- case ImmTyAttrChan: OS << "AttrChan"; break;
+ case ImmTyInterpAttrChan: OS << "InterpAttrChan"; break;
case ImmTyOpSel: OS << "OpSel"; break;
case ImmTyOpSelHi: OS << "OpSelHi"; break;
case ImmTyNegLo: OS << "NegLo"; break;
@@ -7075,8 +7075,8 @@ OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,
AMDGPUOperand::ImmTyInterpAttr));
- Operands.push_back(AMDGPUOperand::CreateImm(this, AttrChan, SChan,
- AMDGPUOperand::ImmTyAttrChan));
+ Operands.push_back(AMDGPUOperand::CreateImm(
+ this, AttrChan, SChan, AMDGPUOperand::ImmTyInterpAttrChan));
return MatchOperand_Success;
}
@@ -8090,9 +8090,8 @@ void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
- } else if (Op.isInterpSlot() ||
- Op.isInterpAttr() ||
- Op.isAttrChan()) {
+ } else if (Op.isInterpSlot() || Op.isInterpAttr() ||
+ Op.isInterpAttrChan()) {
Inst.addOperand(MCOperand::createImm(Op.getImm()));
} else if (Op.isImmModifier()) {
OptionalIdx[Op.getImmTy()] = I;
@@ -9100,10 +9099,10 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;
case MCK_InterpSlot:
return Operand.isInterpSlot() ? Match_Success : Match_InvalidOperand;
- case MCK_Attr:
+ case MCK_InterpAttr:
return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;
- case MCK_AttrChan:
- return Operand.isAttrChan() ? Match_Success : Match_InvalidOperand;
+ case MCK_InterpAttrChan:
+ return Operand.isInterpAttrChan() ? Match_Success : Match_InvalidOperand;
case MCK_SReg_64:
case MCK_SReg_64_XEXEC:
// Null is defined as a 32-bit register but
diff --git a/llvm/lib/Target/AMDGPU/LDSDIRInstructions.td b/llvm/lib/Target/AMDGPU/LDSDIRInstructions.td
index 1f65376890da9..4956a15867749 100644
--- a/llvm/lib/Target/AMDGPU/LDSDIRInstructions.td
+++ b/llvm/lib/Target/AMDGPU/LDSDIRInstructions.td
@@ -34,7 +34,7 @@ class LDSDIRe<bits<2> op, bit is_direct> : Enc32 {
class LDSDIR_getIns<bit direct> {
dag ret = !if(direct,
(ins wait_vdst:$waitvdst),
- (ins Attr:$attr, AttrChan:$attrchan, wait_vdst:$waitvdst)
+ (ins InterpAttr:$attr, InterpAttrChan:$attrchan, wait_vdst:$waitvdst)
);
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index ec9df71ebff84..a2720c9771714 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -935,35 +935,13 @@ def sopp_brtarget : Operand<OtherVT> {
def si_ga : Operand<iPTR>;
-def InterpSlotMatchClass : AsmOperandClass {
- let Name = "InterpSlot";
- let PredicateMethod = "isInterpSlot";
- let ParserMethod = "parseInterpSlot";
- let RenderMethod = "addImmOperands";
-}
-
-def InterpSlot : Operand<i32> {
- let PrintMethod = "printInterpSlot";
- let ParserMatchClass = InterpSlotMatchClass;
- let OperandType = "OPERAND_IMMEDIATE";
-}
-
-def AttrMatchClass : AsmOperandClass {
- let Name = "Attr";
- let PredicateMethod = "isInterpAttr";
- let ParserMethod = "parseInterpAttr";
- let RenderMethod = "addImmOperands";
-}
+def InterpSlot : CustomOperand<i32>;
// It appears to be necessary to create a separate operand for this to
// be able to parse attr<num> with no space.
-def Attr : Operand<i32> {
- let PrintMethod = "printInterpAttr";
- let ParserMatchClass = AttrMatchClass;
- let OperandType = "OPERAND_IMMEDIATE";
-}
+def InterpAttr : CustomOperand<i32>;
-def AttrChan : ImmOperand<i32, "AttrChan", 0, "printInterpAttrChan">;
+def InterpAttrChan : ImmOperand<i32>;
def SendMsgMatchClass : AsmOperandClass {
let Name = "SendMsg";
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 5ffa474857781..c733e04d1d7f9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -47,7 +47,7 @@ let Uses = [MODE, M0, EXEC] in {
multiclass V_INTERP_P1_F32_m : VINTRP_m <
0x00000000,
(outs VINTRPDst:$vdst),
- (ins VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
+ (ins VGPR_32:$vsrc, InterpAttr:$attr, InterpAttrChan:$attrchan),
"v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",
[(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
(i32 timm:$attrchan), (i32 timm:$attr), M0))]
@@ -73,7 +73,8 @@ let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
defm V_INTERP_P2_F32 : VINTRP_m <
0x00000001,
(outs VINTRPDst:$vdst),
- (ins VGPR_32:$src0, VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
+ (ins VGPR_32:$src0, VGPR_32:$vsrc, InterpAttr:$attr,
+ InterpAttrChan:$attrchan),
"v_interp_p2_f32$vdst, $vsrc, $attr$attrchan",
[(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
(i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
@@ -83,7 +84,7 @@ defm V_INTERP_P2_F32 : VINTRP_m <
defm V_INTERP_MOV_F32 : VINTRP_m <
0x00000002,
(outs VINTRPDst:$vdst),
- (ins InterpSlot:$vsrc, Attr:$attr, AttrChan:$attrchan),
+ (ins InterpSlot:$vsrc, InterpAttr:$attr, InterpAttrChan:$attrchan),
"v_interp_mov_f32$vdst, $vsrc, $attr$attrchan",
[(set f32:$vdst, (int_amdgcn_interp_mov (i32 timm:$vsrc),
(i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index b19ae97d4b04b..74bcf94aca12b 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -61,7 +61,7 @@ class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> :
def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
let Src0Mod = FPVRegInputMods;
let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
- Attr:$attr, AttrChan:$attrchan,
+ InterpAttr:$attr, InterpAttrChan:$attrchan,
clampmod0:$clamp, omod0:$omod);
let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
@@ -69,7 +69,7 @@ def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
let Ins64 = (ins InterpSlot:$src0,
- Attr:$attr, AttrChan:$attrchan,
+ InterpAttr:$attr, InterpAttrChan:$attrchan,
clampmod0:$clamp, omod0:$omod);
let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
@@ -90,16 +90,16 @@ class getInterp16Ins <bit HasSrc2, bit HasOMod,
dag ret = !if(HasSrc2,
!if(HasOMod,
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
- Attr:$attr, AttrChan:$attrchan,
+ InterpAttr:$attr, InterpAttrChan:$attrchan,
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
highmod:$high, clampmod0:$clamp, omod0:$omod),
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
- Attr:$attr, AttrChan:$attrchan,
+ InterpAttr:$attr, InterpAttrChan:$attrchan,
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
highmod:$high, clampmod0:$clamp)
),
(ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
- Attr:$attr, AttrChan:$attrchan,
+ InterpAttr:$attr, InterpAttrChan:$attrchan,
highmod:$high, clampmod0:$clamp, omod0:$omod)
);
}
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