[PATCH] D153000: [WIP][RISCV] Make all floating-point instructions SEW-aware

[Wang Pengcheng via Phabricator via llvm-commits]

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For different macroarchtectures, the cost of half, single and double
precision floating-point instructions are different.

So here we make all floating-point arithmetic instructions SEW-aware.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153000

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

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