[llvm] 0a76f7d - [NFC] Autogenerate numerous SystemZ tests
Amaury Séchet via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 14 14:47:59 PDT 2023
Author: Amaury Séchet
Date: 2023-06-14T21:47:31Z
New Revision: 0a76f7d9d8c1fc693568ed26420c47d92a6ba0e7
URL: https://github.com/llvm/llvm-project/commit/0a76f7d9d8c1fc693568ed26420c47d92a6ba0e7
DIFF: https://github.com/llvm/llvm-project/commit/0a76f7d9d8c1fc693568ed26420c47d92a6ba0e7.diff
LOG: [NFC] Autogenerate numerous SystemZ tests
Added:
Modified:
llvm/test/CodeGen/SystemZ/fp-move-02.ll
llvm/test/CodeGen/SystemZ/frame-24.ll
llvm/test/CodeGen/SystemZ/int-move-10.ll
llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll
llvm/test/CodeGen/SystemZ/vec-args-01.ll
llvm/test/CodeGen/SystemZ/vec-args-02.ll
llvm/test/CodeGen/SystemZ/vec-args-03.ll
llvm/test/CodeGen/SystemZ/vec-args-04.ll
llvm/test/CodeGen/SystemZ/vec-args-05.ll
llvm/test/CodeGen/SystemZ/vec-args-07.ll
llvm/test/CodeGen/SystemZ/vec-bswap-01.ll
llvm/test/CodeGen/SystemZ/vec-bswap-02.ll
llvm/test/CodeGen/SystemZ/vec-bswap-03.ll
llvm/test/CodeGen/SystemZ/vec-bswap-04.ll
llvm/test/CodeGen/SystemZ/vec-bswap-05.ll
llvm/test/CodeGen/SystemZ/vec-bswap-06.ll
llvm/test/CodeGen/SystemZ/vec-bswap-07.ll
llvm/test/CodeGen/SystemZ/vec-perm-12.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/SystemZ/fp-move-02.ll b/llvm/test/CodeGen/SystemZ/fp-move-02.ll
index 01e52943bb027..9df852dccbc82 100644
--- a/llvm/test/CodeGen/SystemZ/fp-move-02.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-move-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test moves between FPRs and GPRs. The 32-bit cases test the z10
; implementation, which has no high-word support.
;
@@ -12,8 +13,12 @@ declare double @bar()
; 32 bits of the FPR.
define float @f1(i32 %a) {
; CHECK-LABEL: f1:
-; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 32
-; CHECK: ldgr %f0, [[REGISTER]]
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d
+; CHECK-NEXT: sllg %r0, %r2, 32
+; CHECK-NEXT: ldgr %f0, %r0
+; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d
+; CHECK-NEXT: br %r14
%res = bitcast i32 %a to float
ret float %res
}
@@ -22,8 +27,11 @@ define float @f1(i32 %a) {
; surrounding code.
define float @f2(i64 %big) {
; CHECK-LABEL: f2:
-; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 31
-; CHECK: ldgr %f0, [[REGISTER]]
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r0, %r2, 0, 159, 31
+; CHECK-NEXT: ldgr %f0, %r0
+; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d
+; CHECK-NEXT: br %r14
%shift = lshr i64 %big, 1
%a = trunc i64 %shift to i32
%res = bitcast i32 %a to float
@@ -33,8 +41,11 @@ define float @f2(i64 %big) {
; Another example of the same thing.
define float @f3(i64 %big) {
; CHECK-LABEL: f3:
-; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 2
-; CHECK: ldgr %f0, [[REGISTER]]
+; CHECK: # %bb.0:
+; CHECK-NEXT: risbg %r0, %r2, 0, 159, 2
+; CHECK-NEXT: ldgr %f0, %r0
+; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d
+; CHECK-NEXT: br %r14
%shift = ashr i64 %big, 30
%a = trunc i64 %shift to i32
%res = bitcast i32 %a to float
@@ -44,10 +55,11 @@ define float @f3(i64 %big) {
; Like f1, but the value to transfer is already in the high 32 bits.
define float @f4(i64 %big) {
; CHECK-LABEL: f4:
-; CHECK-NOT: %r2
-; CHECK: nilf %r2, 0
-; CHECK-NOT: %r2
-; CHECK: ldgr %f0, %r2
+; CHECK: # %bb.0:
+; CHECK-NEXT: nilf %r2, 0
+; CHECK-NEXT: ldgr %f0, %r2
+; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d
+; CHECK-NEXT: br %r14
%shift = ashr i64 %big, 32
%a = trunc i64 %shift to i32
%res = bitcast i32 %a to float
@@ -57,7 +69,9 @@ define float @f4(i64 %big) {
; Test 64-bit moves from GPRs to FPRs.
define double @f5(i64 %a) {
; CHECK-LABEL: f5:
-; CHECK: ldgr %f0, %r2
+; CHECK: # %bb.0:
+; CHECK-NEXT: ldgr %f0, %r2
+; CHECK-NEXT: br %r14
%res = bitcast i64 %a to double
ret double %res
}
@@ -66,11 +80,12 @@ define double @f5(i64 %a) {
; so this goes through memory.
define void @f6(ptr %a, ptr %b) {
; CHECK-LABEL: f6:
-; CHECK: lg
-; CHECK: lg
-; CHECK: stg
-; CHECK: stg
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r0, 8(%r3)
+; CHECK-NEXT: lg %r1, 0(%r3)
+; CHECK-NEXT: stg %r0, 8(%r2)
+; CHECK-NEXT: stg %r1, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i128, ptr %b
%res = bitcast i128 %val to fp128
store fp128 %res, ptr %a
@@ -81,8 +96,12 @@ define void @f6(ptr %a, ptr %b) {
; be moved into the low 32 bits of the GPR.
define i32 @f7(float %a) {
; CHECK-LABEL: f7:
-; CHECK: lgdr [[REGISTER:%r[0-5]]], %f0
-; CHECK: srlg %r2, [[REGISTER]], 32
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $f0s killed $f0s def $f0d
+; CHECK-NEXT: lgdr %r0, %f0
+; CHECK-NEXT: srlg %r2, %r0, 32
+; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d
+; CHECK-NEXT: br %r14
%res = bitcast float %a to i32
ret i32 %res
}
@@ -90,7 +109,9 @@ define i32 @f7(float %a) {
; Test 64-bit moves from FPRs to GPRs.
define i64 @f8(double %a) {
; CHECK-LABEL: f8:
-; CHECK: lgdr %r2, %f0
+; CHECK: # %bb.0:
+; CHECK-NEXT: lgdr %r2, %f0
+; CHECK-NEXT: br %r14
%res = bitcast double %a to i64
ret i64 %res
}
@@ -98,10 +119,12 @@ define i64 @f8(double %a) {
; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
define void @f9(ptr %a, ptr %b) {
; CHECK-LABEL: f9:
-; CHECK: ld
-; CHECK: ld
-; CHECK: std
-; CHECK: std
+; CHECK: # %bb.0:
+; CHECK-NEXT: ld %f0, 0(%r2)
+; CHECK-NEXT: ld %f2, 8(%r2)
+; CHECK-NEXT: std %f0, 0(%r3)
+; CHECK-NEXT: std %f2, 8(%r3)
+; CHECK-NEXT: br %r14
%val = load fp128, ptr %a
%res = bitcast fp128 %val to i128
store i128 %res, ptr %b
@@ -112,12 +135,70 @@ define void @f9(ptr %a, ptr %b) {
; We shouldn't have any integer stack stores or floating-point loads.
define void @f10(double %extra) {
; CHECK-LABEL: f10:
-; CHECK: dptr
-; CHECK-NOT: stg {{.*}}(%r15)
-; CHECK: %loop
-; CHECK-NOT: ld {{.*}}(%r15)
-; CHECK: %exit
-; CHECK: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -184
+; CHECK-NEXT: .cfi_def_cfa_offset 344
+; CHECK-NEXT: lgrl %r1, dptr at GOT
+; CHECK-NEXT: ldr %f1, %f0
+; CHECK-NEXT: adb %f1, 0(%r1)
+; CHECK-NEXT: ldr %f2, %f0
+; CHECK-NEXT: adb %f2, 0(%r1)
+; CHECK-NEXT: ldr %f3, %f0
+; CHECK-NEXT: adb %f3, 0(%r1)
+; CHECK-NEXT: std %f1, 176(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f2, 168(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f3, 160(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: ldr %f1, %f0
+; CHECK-NEXT: adb %f1, 0(%r1)
+; CHECK-NEXT: ldr %f2, %f0
+; CHECK-NEXT: adb %f2, 0(%r1)
+; CHECK-NEXT: ldr %f3, %f0
+; CHECK-NEXT: adb %f3, 0(%r1)
+; CHECK-NEXT: ldr %f4, %f0
+; CHECK-NEXT: adb %f4, 0(%r1)
+; CHECK-NEXT: lgdr %r10, %f1
+; CHECK-NEXT: lgdr %r9, %f2
+; CHECK-NEXT: lgdr %r8, %f3
+; CHECK-NEXT: lgdr %r7, %f4
+; CHECK-NEXT: ldr %f1, %f0
+; CHECK-NEXT: adb %f1, 0(%r1)
+; CHECK-NEXT: ldr %f2, %f0
+; CHECK-NEXT: adb %f2, 0(%r1)
+; CHECK-NEXT: adb %f0, 0(%r1)
+; CHECK-NEXT: lgrl %r6, iptr at GOT
+; CHECK-NEXT: lgdr %r13, %f1
+; CHECK-NEXT: lgdr %r12, %f2
+; CHECK-NEXT: lgdr %r11, %f0
+; CHECK-NEXT: .LBB9_1: # %loop
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: lgr %r0, %r2
+; CHECK-NEXT: og %r0, 176(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: og %r0, 168(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: og %r0, 160(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ogr %r0, %r10
+; CHECK-NEXT: ogr %r0, %r9
+; CHECK-NEXT: ogr %r0, %r8
+; CHECK-NEXT: ogr %r0, %r7
+; CHECK-NEXT: ogr %r0, %r13
+; CHECK-NEXT: ogr %r0, %r12
+; CHECK-NEXT: ogr %r0, %r11
+; CHECK-NEXT: stg %r0, 0(%r6)
+; CHECK-NEXT: cgijlh %r2, 1, .LBB9_1
+; CHECK-NEXT: # %bb.2: # %exit
+; CHECK-NEXT: lmg %r6, %r15, 232(%r15)
+; CHECK-NEXT: br %r14
entry:
%double0 = load volatile double, ptr at dptr
%biased0 = fadd double %double0, %extra
@@ -174,12 +255,90 @@ exit:
; ...likewise LDGR, with the requirements the other way around.
define void @f11(i64 %mask) {
; CHECK-LABEL: f11:
-; CHECK: iptr
-; CHECK-NOT: std {{.*}}(%r15)
-; CHECK: %loop
-; CHECK-NOT: lg {{.*}}(%r15)
-; CHECK: %exit
-; CHECK: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r12, %r15, 96(%r15)
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -240
+; CHECK-NEXT: .cfi_def_cfa_offset 400
+; CHECK-NEXT: std %f8, 232(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f9, 224(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f10, 216(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f11, 208(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f12, 200(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f13, 192(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f14, 184(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f15, 176(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset %f8, -168
+; CHECK-NEXT: .cfi_offset %f9, -176
+; CHECK-NEXT: .cfi_offset %f10, -184
+; CHECK-NEXT: .cfi_offset %f11, -192
+; CHECK-NEXT: .cfi_offset %f12, -200
+; CHECK-NEXT: .cfi_offset %f13, -208
+; CHECK-NEXT: .cfi_offset %f14, -216
+; CHECK-NEXT: .cfi_offset %f15, -224
+; CHECK-NEXT: lgrl %r1, iptr at GOT
+; CHECK-NEXT: lgr %r0, %r2
+; CHECK-NEXT: ng %r0, 0(%r1)
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: ng %r3, 0(%r1)
+; CHECK-NEXT: lgr %r4, %r2
+; CHECK-NEXT: ng %r4, 0(%r1)
+; CHECK-NEXT: stg %r0, 168(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: stg %r3, 160(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: lgr %r0, %r2
+; CHECK-NEXT: ng %r0, 0(%r1)
+; CHECK-NEXT: ldgr %f10, %r4
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: ng %r3, 0(%r1)
+; CHECK-NEXT: lgr %r4, %r2
+; CHECK-NEXT: ng %r4, 0(%r1)
+; CHECK-NEXT: ldgr %f11, %r0
+; CHECK-NEXT: lgr %r0, %r2
+; CHECK-NEXT: ng %r0, 0(%r1)
+; CHECK-NEXT: ldgr %f12, %r3
+; CHECK-NEXT: ldgr %f13, %r4
+; CHECK-NEXT: lgr %r3, %r2
+; CHECK-NEXT: ng %r3, 0(%r1)
+; CHECK-NEXT: ldgr %f14, %r0
+; CHECK-NEXT: lgr %r0, %r2
+; CHECK-NEXT: ng %r0, 0(%r1)
+; CHECK-NEXT: ng %r2, 0(%r1)
+; CHECK-NEXT: ldgr %f15, %r3
+; CHECK-NEXT: lgrl %r13, dptr at GOT
+; CHECK-NEXT: ldgr %f8, %r0
+; CHECK-NEXT: ldgr %f9, %r2
+; CHECK-NEXT: larl %r12, .LCPI10_0
+; CHECK-NEXT: .LBB10_1: # %loop
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: brasl %r14, bar at PLT
+; CHECK-NEXT: ldr %f1, %f0
+; CHECK-NEXT: adb %f1, 168(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: adb %f1, 160(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: adbr %f1, %f10
+; CHECK-NEXT: adbr %f1, %f11
+; CHECK-NEXT: adbr %f1, %f12
+; CHECK-NEXT: adbr %f1, %f13
+; CHECK-NEXT: adbr %f1, %f14
+; CHECK-NEXT: adbr %f1, %f15
+; CHECK-NEXT: adbr %f1, %f8
+; CHECK-NEXT: adbr %f1, %f9
+; CHECK-NEXT: cdb %f0, 0(%r12)
+; CHECK-NEXT: std %f1, 0(%r13)
+; CHECK-NEXT: jlh .LBB10_1
+; CHECK-NEXT: # %bb.2: # %exit
+; CHECK-NEXT: ld %f8, 232(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f9, 224(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f10, 216(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f11, 208(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f12, 200(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f13, 192(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f14, 184(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f15, 176(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: lmg %r12, %r15, 336(%r15)
+; CHECK-NEXT: br %r14
entry:
%int0 = load volatile i64, ptr at iptr
%masked0 = and i64 %int0, %mask
@@ -237,13 +396,85 @@ exit:
; We shouldn't have any integer stack stores or floating-point loads.
define void @f12() {
; CHECK-LABEL: f12:
-; CHECK: %loop
-; CHECK-NOT: std {{.*}}(%r15)
-; CHECK: %exit
-; CHECK: foo at PLT
-; CHECK-NOT: lg {{.*}}(%r15)
-; CHECK: foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lghi %r12, 0
+; CHECK-NEXT: lghi %r13, 0
+; CHECK-NEXT: lghi %r6, 0
+; CHECK-NEXT: lghi %r7, 0
+; CHECK-NEXT: lghi %r8, 0
+; CHECK-NEXT: lghi %r9, 0
+; CHECK-NEXT: lghi %r10, 0
+; CHECK-NEXT: lghi %r11, 0
+; CHECK-NEXT: mvghi 160(%r15), 0 # 8-byte Folded Spill
+; CHECK-NEXT: mvghi 168(%r15), 0 # 8-byte Folded Spill
+; CHECK-NEXT: .LBB11_1: # %loop
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: agr %r12, %r2
+; CHECK-NEXT: agr %r13, %r2
+; CHECK-NEXT: agr %r6, %r2
+; CHECK-NEXT: agr %r7, %r2
+; CHECK-NEXT: agr %r8, %r2
+; CHECK-NEXT: agr %r9, %r2
+; CHECK-NEXT: agr %r10, %r2
+; CHECK-NEXT: agr %r11, %r2
+; CHECK-NEXT: lg %r0, 160(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: agr %r0, %r2
+; CHECK-NEXT: stg %r0, 160(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: lg %r0, 168(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: agr %r0, %r2
+; CHECK-NEXT: stg %r0, 168(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: cgijlh %r2, 1, .LBB11_1
+; CHECK-NEXT: # %bb.2: # %exit
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: lgrl %r1, dptr at GOT
+; CHECK-NEXT: ld %f0, 0(%r1)
+; CHECK-NEXT: ldgr %f1, %r12
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: ldgr %f1, %r13
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: ldgr %f1, %r6
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: ldgr %f1, %r7
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: ldgr %f1, %r8
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: ldgr %f1, %r9
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: ldgr %f1, %r10
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: ldgr %f1, %r11
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: ld %f1, 160(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: ld %f1, 168(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 0(%r1)
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: lmg %r6, %r15, 224(%r15)
+; CHECK-NEXT: br %r14
entry:
br label %loop
@@ -316,13 +547,104 @@ exit:
; ...likewise LGDR, with the requirements the other way around.
define void @f13() {
; CHECK-LABEL: f13:
-; CHECK: %loop
-; CHECK-NOT: stg {{.*}}(%r15)
-; CHECK: %exit
-; CHECK: foo at PLT
-; CHECK-NOT: ld {{.*}}(%r15)
-; CHECK: foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -240
+; CHECK-NEXT: .cfi_def_cfa_offset 400
+; CHECK-NEXT: std %f8, 232(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f9, 224(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f10, 216(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f11, 208(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f12, 200(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f13, 192(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f14, 184(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f15, 176(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset %f8, -168
+; CHECK-NEXT: .cfi_offset %f9, -176
+; CHECK-NEXT: .cfi_offset %f10, -184
+; CHECK-NEXT: .cfi_offset %f11, -192
+; CHECK-NEXT: .cfi_offset %f12, -200
+; CHECK-NEXT: .cfi_offset %f13, -208
+; CHECK-NEXT: .cfi_offset %f14, -216
+; CHECK-NEXT: .cfi_offset %f15, -224
+; CHECK-NEXT: larl %r13, .LCPI12_0
+; CHECK-NEXT: ld %f8, 0(%r13)
+; CHECK-NEXT: ldr %f9, %f8
+; CHECK-NEXT: ldr %f15, %f8
+; CHECK-NEXT: ldr %f14, %f8
+; CHECK-NEXT: ldr %f13, %f8
+; CHECK-NEXT: ldr %f12, %f8
+; CHECK-NEXT: ldr %f11, %f8
+; CHECK-NEXT: ldr %f10, %f8
+; CHECK-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f8, 168(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: .LBB12_1: # %loop
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: brasl %r14, bar at PLT
+; CHECK-NEXT: mdbr %f8, %f0
+; CHECK-NEXT: mdbr %f9, %f0
+; CHECK-NEXT: mdbr %f15, %f0
+; CHECK-NEXT: mdbr %f14, %f0
+; CHECK-NEXT: mdbr %f13, %f0
+; CHECK-NEXT: mdbr %f12, %f0
+; CHECK-NEXT: cdb %f0, 0(%r13)
+; CHECK-NEXT: mdbr %f11, %f0
+; CHECK-NEXT: mdbr %f10, %f0
+; CHECK-NEXT: ld %f1, 160(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 160(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: ld %f1, 168(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: mdbr %f1, %f0
+; CHECK-NEXT: std %f1, 168(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: jlh .LBB12_1
+; CHECK-NEXT: # %bb.2: # %exit
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: lgrl %r1, iptr at GOT
+; CHECK-NEXT: lg %r0, 0(%r1)
+; CHECK-NEXT: lgdr %r2, %f8
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: lgdr %r2, %f9
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: lgdr %r2, %f15
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: lgdr %r2, %f14
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: lgdr %r2, %f13
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: lgdr %r2, %f12
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: lgdr %r2, %f11
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: lgdr %r2, %f10
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: lg %r2, 160(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: lg %r2, 168(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: agr %r2, %r0
+; CHECK-NEXT: stg %r2, 0(%r1)
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: ld %f8, 232(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f9, 224(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f10, 216(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f11, 208(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f12, 200(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f13, 192(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f14, 184(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f15, 176(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: lmg %r13, %r15, 344(%r15)
+; CHECK-NEXT: br %r14
entry:
br label %loop
diff --git a/llvm/test/CodeGen/SystemZ/frame-24.ll b/llvm/test/CodeGen/SystemZ/frame-24.ll
index bfa74552508c0..7ceb9beec54ae 100644
--- a/llvm/test/CodeGen/SystemZ/frame-24.ll
+++ b/llvm/test/CodeGen/SystemZ/frame-24.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
;
; Test saving of vararg registers and backchain with packed stack.
@@ -8,19 +9,20 @@ declare void @llvm.va_start(ptr)
attributes #0 = { nounwind "packed-stack"="true" }
define void @fun0(i64 %g0, double %d0, i64 %n, ...) #0 {
; CHECK-LABEL: fun0:
-; CHECK: stmg %r4, %r15, 32(%r15)
-; CHECK-NEXT: aghi %r15, -192
-; CHECK-NEXT: std %f2, 328(%r15)
-; CHECK-NEXT: std %f4, 336(%r15)
-; CHECK-NEXT: std %f6, 344(%r15)
-; CHECK-NEXT: la %r0, 352(%r15)
-; CHECK-NEXT: stg %r0, 176(%r15)
-; CHECK-NEXT: la %r0, 192(%r15)
-; CHECK-NEXT: stg %r0, 184(%r15)
-; CHECK-NEXT: mvghi 160(%r15), 2
-; CHECK-NEXT: mvghi 168(%r15), 1
-; CHECK-NEXT: lmg %r6, %r15, 240(%r15)
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r4, %r15, 32(%r15)
+; CHECK-NEXT: aghi %r15, -192
+; CHECK-NEXT: std %f2, 328(%r15)
+; CHECK-NEXT: std %f4, 336(%r15)
+; CHECK-NEXT: std %f6, 344(%r15)
+; CHECK-NEXT: la %r0, 352(%r15)
+; CHECK-NEXT: stg %r0, 176(%r15)
+; CHECK-NEXT: la %r0, 192(%r15)
+; CHECK-NEXT: stg %r0, 184(%r15)
+; CHECK-NEXT: mvghi 160(%r15), 2
+; CHECK-NEXT: mvghi 168(%r15), 1
+; CHECK-NEXT: lmg %r6, %r15, 240(%r15)
+; CHECK-NEXT: br %r14
entry:
%vl = alloca [1 x %struct.__va_list_tag], align 8
call void @llvm.va_start(ptr nonnull %vl)
@@ -30,16 +32,17 @@ entry:
attributes #1 = { nounwind "packed-stack"="true" "use-soft-float"="true" }
define void @fun1(i64 %g0, double %d0, i64 %n, ...) #1 {
; CHECK-LABEL: fun1:
-; CHECK: stmg %r5, %r15, 72(%r15)
-; CHECK-NEXT: aghi %r15, -160
-; CHECK-NEXT: la %r0, 192(%r15)
-; CHECK-NEXT: stg %r0, 184(%r15)
-; CHECK-NEXT: la %r0, 320(%r15)
-; CHECK-NEXT: stg %r0, 176(%r15)
-; CHECK-NEXT: mvghi 168(%r15), 0
-; CHECK-NEXT: mvghi 160(%r15), 3
-; CHECK-NEXT: lmg %r6, %r15, 240(%r15)
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r5, %r15, 72(%r15)
+; CHECK-NEXT: aghi %r15, -160
+; CHECK-NEXT: la %r0, 192(%r15)
+; CHECK-NEXT: stg %r0, 184(%r15)
+; CHECK-NEXT: la %r0, 320(%r15)
+; CHECK-NEXT: stg %r0, 176(%r15)
+; CHECK-NEXT: mvghi 168(%r15), 0
+; CHECK-NEXT: mvghi 160(%r15), 3
+; CHECK-NEXT: lmg %r6, %r15, 240(%r15)
+; CHECK-NEXT: br %r14
entry:
%vl = alloca [1 x %struct.__va_list_tag], align 8
call void @llvm.va_start(ptr nonnull %vl)
@@ -49,18 +52,19 @@ entry:
attributes #2 = { nounwind "packed-stack"="true" "use-soft-float"="true" "backchain"}
define void @fun2(i64 %g0, double %d0, i64 %n, ...) #2 {
; CHECK-LABEL: fun2:
-; CHECK: stmg %r5, %r15, 64(%r15)
-; CHECK-NEXT: lgr %r1, %r15
-; CHECK-NEXT: aghi %r15, -168
-; CHECK-NEXT: stg %r1, 152(%r15)
-; CHECK-NEXT: la %r0, 192(%r15)
-; CHECK-NEXT: stg %r0, 184(%r15)
-; CHECK-NEXT: la %r0, 328(%r15)
-; CHECK-NEXT: stg %r0, 176(%r15)
-; CHECK-NEXT: mvghi 168(%r15), 0
-; CHECK-NEXT: mvghi 160(%r15), 3
-; CHECK-NEXT: lmg %r6, %r15, 240(%r15)
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r5, %r15, 64(%r15)
+; CHECK-NEXT: lgr %r1, %r15
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: stg %r1, 152(%r15)
+; CHECK-NEXT: la %r0, 192(%r15)
+; CHECK-NEXT: stg %r0, 184(%r15)
+; CHECK-NEXT: la %r0, 328(%r15)
+; CHECK-NEXT: stg %r0, 176(%r15)
+; CHECK-NEXT: mvghi 168(%r15), 0
+; CHECK-NEXT: mvghi 160(%r15), 3
+; CHECK-NEXT: lmg %r6, %r15, 240(%r15)
+; CHECK-NEXT: br %r14
entry:
%vl = alloca [1 x %struct.__va_list_tag], align 8
call void @llvm.va_start(ptr nonnull %vl)
diff --git a/llvm/test/CodeGen/SystemZ/int-move-10.ll b/llvm/test/CodeGen/SystemZ/int-move-10.ll
index 4ae5d05a2e84a..a3b0371285704 100644
--- a/llvm/test/CodeGen/SystemZ/int-move-10.ll
+++ b/llvm/test/CodeGen/SystemZ/int-move-10.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
;
; Test PC-relative memory accesses of globals with packed struct types.
@@ -34,9 +35,10 @@
; unaligned packed struct + 2 -> unaligned address
define dso_local void @f1() {
; CHECK-LABEL: f1:
-; CHECK: larl %r1, A_align2
-; CHECK: mvhi 2(%r1), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, A_align2
+; CHECK-NEXT: mvhi 2(%r1), 0
+; CHECK-NEXT: br %r14
store i32 0, ptr getelementptr inbounds (%packed.i16i32, ptr @A_align2, i64 0, i32 1), align 4
ret void
}
@@ -44,9 +46,10 @@ define dso_local void @f1() {
; unaligned packed struct + 8 -> unaligned address
define dso_local void @f2() {
; CHECK-LABEL: f2:
-; CHECK: larl %r1, B_align2
-; CHECK: mvhi 8(%r1), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, B_align2
+; CHECK-NEXT: mvhi 8(%r1), 0
+; CHECK-NEXT: br %r14
store i32 0, ptr getelementptr inbounds (%packed.i16i32i16i32, ptr @B_align2, i64 0, i32 3), align 4
ret void
}
@@ -54,9 +57,10 @@ define dso_local void @f2() {
; aligned packed struct + 2 -> unaligned address
define dso_local void @f3() {
; CHECK-LABEL: f3:
-; CHECK: larl %r1, D_align4
-; CHECK: mvhi 2(%r1), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, D_align4
+; CHECK-NEXT: mvhi 2(%r1), 0
+; CHECK-NEXT: br %r14
store i32 0, ptr getelementptr inbounds (%packed.i16i32, ptr @D_align4, i64 0, i32 1), align 4
ret void
}
@@ -64,35 +68,41 @@ define dso_local void @f3() {
; aligned packed struct + 8 -> aligned address
define dso_local void @f4() {
; CHECK-LABEL: f4:
-; CHECK: lhi %r0, 0
-; CHECK: strl %r0, E_align4+8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lhi %r0, 0
+; CHECK-NEXT: strl %r0, E_align4+8
+; CHECK-NEXT: br %r14
store i32 0, ptr getelementptr inbounds (%packed.i16i32i16i32, ptr @E_align4, i64 0, i32 3), align 4
ret void
}
define dso_local void @f5() {
; CHECK-LABEL: f5:
-; CHECK: larl %r1, C_align2
-; CHECK: mvghi 2(%r1), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, C_align2
+; CHECK-NEXT: mvghi 2(%r1), 0
+; CHECK-NEXT: br %r14
store i64 0, ptr getelementptr inbounds (%packed.i16i64, ptr @C_align2, i64 0, i32 1), align 8
ret void
}
define dso_local void @f6() {
; CHECK-LABEL: f6:
-; CHECK-NOT: sthrl
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, F_align2
+; CHECK-NEXT: mvhhi 1(%r1), 0
+; CHECK-NEXT: br %r14
store i16 0, ptr getelementptr inbounds (%packed.i8i16, ptr @F_align2, i64 0, i32 1), align 2
ret void
}
define dso_local void @f7(ptr %Src) {
; CHECK-LABEL: f7:
-; CHECK: lg %r0, 0(%r2)
-; CHECK: larl %r1, D_align4
-; CHECK: st %r0, 2(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r0, 0(%r2)
+; CHECK-NEXT: larl %r1, D_align4
+; CHECK-NEXT: st %r0, 2(%r1)
+; CHECK-NEXT: br %r14
%L = load i64, ptr %Src
%T = trunc i64 %L to i32
store i32 %T, ptr getelementptr inbounds (%packed.i16i32, ptr @D_align4, i64 0, i32 1), align 4
@@ -101,7 +111,11 @@ define dso_local void @f7(ptr %Src) {
define dso_local void @f8(ptr %Src) {
; CHECK-LABEL: f8:
-; CHECK-NOT: sthrl
+; CHECK: # %bb.0:
+; CHECK-NEXT: lg %r0, 0(%r2)
+; CHECK-NEXT: larl %r1, F_align2
+; CHECK-NEXT: sth %r0, 1(%r1)
+; CHECK-NEXT: br %r14
%L = load i64, ptr %Src
%T = trunc i64 %L to i16
store i16 %T, ptr getelementptr inbounds (%packed.i8i16, ptr @F_align2, i64 0, i32 1), align 2
@@ -113,9 +127,10 @@ define dso_local void @f8(ptr %Src) {
; unaligned packed struct + 2 -> unaligned address
define dso_local i32 @f9() {
; CHECK-LABEL: f9:
-; CHECK: larl %r1, A_align2
-; CHECK: l %r2, 2(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, A_align2
+; CHECK-NEXT: l %r2, 2(%r1)
+; CHECK-NEXT: br %r14
%L = load i32, ptr getelementptr inbounds (%packed.i16i32, ptr @A_align2, i64 0, i32 1), align 4
ret i32 %L
}
@@ -123,9 +138,10 @@ define dso_local i32 @f9() {
; unaligned packed struct + 8 -> unaligned address
define dso_local i32 @f10() {
; CHECK-LABEL: f10:
-; CHECK: larl %r1, B_align2
-; CHECK: l %r2, 8(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, B_align2
+; CHECK-NEXT: l %r2, 8(%r1)
+; CHECK-NEXT: br %r14
%L = load i32, ptr getelementptr inbounds (%packed.i16i32i16i32, ptr @B_align2, i64 0, i32 3), align 4
ret i32 %L
}
@@ -133,9 +149,10 @@ define dso_local i32 @f10() {
; aligned packed struct + 2 -> unaligned address
define dso_local i32 @f11() {
; CHECK-LABEL: f11:
-; CHECK: larl %r1, D_align4
-; CHECK: l %r2, 2(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, D_align4
+; CHECK-NEXT: l %r2, 2(%r1)
+; CHECK-NEXT: br %r14
%L = load i32, ptr getelementptr inbounds (%packed.i16i32, ptr @D_align4, i64 0, i32 1), align 4
ret i32 %L
}
@@ -143,24 +160,29 @@ define dso_local i32 @f11() {
; aligned packed struct + 8 -> aligned address
define dso_local i32 @f12() {
; CHECK-LABEL: f12:
-; CHECK: lrl %r2, E_align4+8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lrl %r2, E_align4+8
+; CHECK-NEXT: br %r14
%L = load i32, ptr getelementptr inbounds (%packed.i16i32i16i32, ptr @E_align4, i64 0, i32 3), align 4
ret i32 %L
}
define dso_local i64 @f13() {
; CHECK-LABEL: f13:
-; CHECK: larl %r1, C_align2
-; CHECK: lg %r2, 2(%r1)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, C_align2
+; CHECK-NEXT: lg %r2, 2(%r1)
+; CHECK-NEXT: br %r14
%L = load i64, ptr getelementptr inbounds (%packed.i16i64, ptr @C_align2, i64 0, i32 1), align 8
ret i64 %L
}
define dso_local i32 @f14() {
; CHECK-LABEL: f14:
-; CHECK-NOT: lhrl
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, F_align2
+; CHECK-NEXT: lh %r2, 1(%r1)
+; CHECK-NEXT: br %r14
%L = load i16, ptr getelementptr inbounds (%packed.i8i16, ptr @F_align2, i64 0, i32 1), align 2
%ext = sext i16 %L to i32
ret i32 %ext
@@ -168,7 +190,10 @@ define dso_local i32 @f14() {
define dso_local i64 @f15() {
; CHECK-LABEL: f15:
-; CHECK-NOT: llghrl
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, F_align2
+; CHECK-NEXT: llgh %r2, 1(%r1)
+; CHECK-NEXT: br %r14
%L = load i16, ptr getelementptr inbounds (%packed.i8i16, ptr @F_align2, i64 0, i32 1), align 2
%ext = zext i16 %L to i64
ret i64 %ext
@@ -178,8 +203,13 @@ define dso_local i64 @f15() {
define dso_local i32 @f16(i32 %src1) {
; CHECK-LABEL: f16:
-; CHECK: larl %r1, A_align2
-; CHECK: c %r2, 2(%r1)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: larl %r1, A_align2
+; CHECK-NEXT: c %r2, 2(%r1)
+; CHECK-NEXT: blr %r14
+; CHECK-NEXT: .LBB15_1: # %mulb
+; CHECK-NEXT: msr %r2, %r2
+; CHECK-NEXT: br %r14
entry:
%src2 = load i32, ptr getelementptr inbounds (%packed.i16i32, ptr @A_align2, i64 0, i32 1), align 4
%cond = icmp slt i32 %src1, %src2
@@ -194,8 +224,13 @@ exit:
define dso_local i64 @f17(i64 %src1) {
; CHECK-LABEL: f17:
-; CHECK: larl %r1, C_align2
-; CHECK: clg %r2, 2(%r1)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: larl %r1, C_align2
+; CHECK-NEXT: clg %r2, 2(%r1)
+; CHECK-NEXT: blr %r14
+; CHECK-NEXT: .LBB16_1: # %mulb
+; CHECK-NEXT: msgr %r2, %r2
+; CHECK-NEXT: br %r14
entry:
%src2 = load i64, ptr getelementptr inbounds (%packed.i16i64, ptr @C_align2, i64 0, i32 1), align 8
%cond = icmp ult i64 %src1, %src2
diff --git a/llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll b/llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll
index 1fc14964a94a9..4ad7e33ea2d82 100644
--- a/llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll
+++ b/llvm/test/CodeGen/SystemZ/signbits-intrinsics-binop.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test that DAGCombiner gets helped by ComputeNumSignBitsForTargetNode() with
; vector intrinsics.
;
@@ -10,9 +11,11 @@ declare {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64>, <2 x i64>)
; PACKS_CC: i64 -> i32
define <4 x i32> @f0() {
; CHECK-LABEL: f0:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpksgs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI0_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vpksgs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> <i64 0, i64 1>, <2 x i64> <i64 0, i64 1>)
%extr = extractvalue {<4 x i32>, i32} %call, 0
%trunc = trunc <4 x i32> %extr to <4 x i16>
@@ -23,9 +26,11 @@ define <4 x i32> @f0() {
; PACKS_CC: i32 -> i16
define <8 x i16> @f1() {
; CHECK-LABEL: f1:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpksfs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI1_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vpksfs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> <i32 0, i32 1, i32 1, i32 0>,
<4 x i32> <i32 0, i32 1, i32 1, i32 0>)
%extr = extractvalue {<8 x i16>, i32} %call, 0
@@ -37,9 +42,11 @@ define <8 x i16> @f1() {
; PACKS_CC: i16 -> i8
define <16 x i8> @f2() {
; CHECK-LABEL: f2:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpkshs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI2_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vpkshs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vpkshs(
<8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 0, i16 0, i16 1, i16 1>,
<8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 0, i16 0, i16 1, i16 1>)
@@ -56,9 +63,13 @@ declare {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64>, <2 x i64>)
; PACKLS_CC: i64 -> i32
define <4 x i32> @f3() {
; CHECK-LABEL: f3:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpklsgs %v24, %v1, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI3_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: larl %r1, .LCPI3_1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vpklsgs %v24, %v1, %v0
+; CHECK-NEXT: br %r14
%call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> <i64 0, i64 1>, <2 x i64> <i64 1, i64 0>)
%extr = extractvalue {<4 x i32>, i32} %call, 0
%trunc = trunc <4 x i32> %extr to <4 x i16>
@@ -69,9 +80,11 @@ define <4 x i32> @f3() {
; PACKLS_CC: i32 -> i16
define <8 x i16> @f4() {
; CHECK-LABEL: f4:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpklsfs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI4_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vpklsfs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> <i32 0, i32 1, i32 1, i32 0>,
<4 x i32> <i32 0, i32 1, i32 1, i32 0>)
%extr = extractvalue {<8 x i16>, i32} %call, 0
@@ -83,9 +96,11 @@ define <8 x i16> @f4() {
; PACKLS_CC: i16 -> i8
define <16 x i8> @f5() {
; CHECK-LABEL: f5:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpklshs %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI5_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vpklshs %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call {<16 x i8>, i32} @llvm.s390.vpklshs(
<8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 0, i16 0, i16 1, i16 1>,
<8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 0, i16 0, i16 1, i16 1>)
@@ -102,9 +117,13 @@ declare <4 x i32> @llvm.s390.vpksg(<2 x i64>, <2 x i64>)
; PACKS: i64 -> i32
define <4 x i32> @f6() {
; CHECK-LABEL: f6:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpksg %v24, %v1, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI6_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: larl %r1, .LCPI6_1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vpksg %v24, %v1, %v0
+; CHECK-NEXT: br %r14
%call = call <4 x i32> @llvm.s390.vpksg(<2 x i64> <i64 0, i64 1>, <2 x i64> <i64 1, i64 0>)
%trunc = trunc <4 x i32> %call to <4 x i16>
%ret = sext <4 x i16> %trunc to <4 x i32>
@@ -114,9 +133,11 @@ define <4 x i32> @f6() {
; PACKS: i32 -> i16
define <8 x i16> @f7() {
; CHECK-LABEL: f7:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpksf %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI7_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vpksf %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <8 x i16> @llvm.s390.vpksf(<4 x i32> <i32 0, i32 1, i32 1, i32 0>,
<4 x i32> <i32 0, i32 1, i32 1, i32 0>)
%trunc = trunc <8 x i16> %call to <8 x i8>
@@ -127,9 +148,11 @@ define <8 x i16> @f7() {
; PACKS: i16 -> i8
define <16 x i8> @f8() {
; CHECK-LABEL: f8:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpksh %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI8_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vpksh %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <16 x i8> @llvm.s390.vpksh(
<8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 0, i16 0, i16 1, i16 1>,
<8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 0, i16 0, i16 1, i16 1>)
@@ -145,9 +168,13 @@ declare <4 x i32> @llvm.s390.vpklsg(<2 x i64>, <2 x i64>)
; PACKLS: i64 -> i32
define <4 x i32> @f9() {
; CHECK-LABEL: f9:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpklsg %v24, %v1, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI9_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: larl %r1, .LCPI9_1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vpklsg %v24, %v1, %v0
+; CHECK-NEXT: br %r14
%call = call <4 x i32> @llvm.s390.vpklsg(<2 x i64> <i64 0, i64 1>, <2 x i64> <i64 1, i64 0>)
%trunc = trunc <4 x i32> %call to <4 x i16>
%ret = sext <4 x i16> %trunc to <4 x i32>
@@ -157,9 +184,11 @@ define <4 x i32> @f9() {
; PACKLS: i32 -> i16
define <8 x i16> @f10() {
; CHECK-LABEL: f10:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpklsf %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI10_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vpklsf %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <8 x i16> @llvm.s390.vpklsf(<4 x i32> <i32 0, i32 1, i32 1, i32 0>,
<4 x i32> <i32 0, i32 1, i32 1, i32 0>)
%trunc = trunc <8 x i16> %call to <8 x i8>
@@ -170,9 +199,11 @@ define <8 x i16> @f10() {
; PACKLS: i16 -> i8
define <16 x i8> @f11() {
; CHECK-LABEL: f11:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpklsh %v24, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI11_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vpklsh %v24, %v0, %v0
+; CHECK-NEXT: br %r14
%call = call <16 x i8> @llvm.s390.vpklsh(
<8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 0, i16 0, i16 1, i16 1>,
<8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 0, i16 0, i16 1, i16 1>)
@@ -186,9 +217,13 @@ declare <2 x i64> @llvm.s390.vpdi(<2 x i64>, <2 x i64>, i32)
; VPDI:
define <2 x i64> @f12() {
; CHECK-LABEL: f12:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vpdi %v24, %v1, %v0, 0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI12_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: larl %r1, .LCPI12_1
+; CHECK-NEXT: vl %v1, 0(%r1), 3
+; CHECK-NEXT: vpdi %v24, %v1, %v0, 0
+; CHECK-NEXT: br %r14
%perm = call <2 x i64> @llvm.s390.vpdi(<2 x i64> <i64 0, i64 1>,
<2 x i64> <i64 1, i64 0>, i32 0)
%trunc = trunc <2 x i64> %perm to <2 x i32>
@@ -201,9 +236,11 @@ declare <16 x i8> @llvm.s390.vsldb(<16 x i8>, <16 x i8>, i32)
; VSLDB:
define <16 x i8> @f13() {
; CHECK-LABEL: f13:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vsldb %v24, %v0, %v0, 1
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI13_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vsldb %v24, %v0, %v0, 1
+; CHECK-NEXT: br %r14
%shfd = call <16 x i8> @llvm.s390.vsldb(<16 x i8>
<i8 0, i8 0, i8 1, i8 1, i8 0, i8 1, i8 1, i8 1,
i8 0, i8 0, i8 1, i8 1, i8 0, i8 1, i8 1, i8 1>, <16 x i8>
@@ -220,9 +257,11 @@ declare <16 x i8> @llvm.s390.vperm(<16 x i8>, <16 x i8>, <16 x i8>)
; Test VPERM:
define <16 x i8> @f14() {
; CHECK-LABEL: f14:
-; CHECK-LABEL: # %bb.0:
-; CHECK: vperm %v24, %v0, %v0, %v0
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: larl %r1, .LCPI14_0
+; CHECK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-NEXT: vperm %v24, %v0, %v0, %v0
+; CHECK-NEXT: br %r14
%perm = call <16 x i8> @llvm.s390.vperm(
<16 x i8> <i8 0, i8 0, i8 1, i8 1, i8 0, i8 1, i8 1, i8 1,
i8 0, i8 0, i8 1, i8 1, i8 0, i8 1, i8 1, i8 1>,
diff --git a/llvm/test/CodeGen/SystemZ/vec-args-01.ll b/llvm/test/CodeGen/SystemZ/vec-args-01.ll
index e07ab7447b2a9..729698c1966b5 100644
--- a/llvm/test/CodeGen/SystemZ/vec-args-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-args-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test the handling of named vector arguments.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
@@ -14,24 +15,64 @@ declare void @bar(i64, i64, i64, i64, i64, i64,
define void @foo() {
; CHECK-VEC-LABEL: foo:
-; CHECK-VEC-DAG: vrepif %v24, 1
-; CHECK-VEC-DAG: vrepif %v26, 2
-; CHECK-VEC-DAG: vrepif %v28, 3
-; CHECK-VEC-DAG: vrepif %v30, 4
-; CHECK-VEC-DAG: vrepif %v25, 5
-; CHECK-VEC-DAG: vrepif %v27, 6
-; CHECK-VEC-DAG: vrepif %v29, 7
-; CHECK-VEC-DAG: vrepif %v31, 8
-; CHECK-VEC: brasl %r14, bar at PLT
+; CHECK-VEC: # %bb.0:
+; CHECK-VEC-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-VEC-NEXT: .cfi_offset %r6, -112
+; CHECK-VEC-NEXT: .cfi_offset %r14, -48
+; CHECK-VEC-NEXT: .cfi_offset %r15, -40
+; CHECK-VEC-NEXT: aghi %r15, -200
+; CHECK-VEC-NEXT: .cfi_def_cfa_offset 360
+; CHECK-VEC-NEXT: vrepif %v0, 10
+; CHECK-VEC-NEXT: vst %v0, 184(%r15), 3
+; CHECK-VEC-NEXT: vrepif %v0, 9
+; CHECK-VEC-NEXT: vrepif %v24, 1
+; CHECK-VEC-NEXT: vrepif %v26, 2
+; CHECK-VEC-NEXT: vrepif %v28, 3
+; CHECK-VEC-NEXT: vrepif %v30, 4
+; CHECK-VEC-NEXT: vrepif %v25, 5
+; CHECK-VEC-NEXT: vrepif %v27, 6
+; CHECK-VEC-NEXT: vrepif %v29, 7
+; CHECK-VEC-NEXT: vrepif %v31, 8
+; CHECK-VEC-NEXT: lghi %r2, 1
+; CHECK-VEC-NEXT: lghi %r3, 2
+; CHECK-VEC-NEXT: lghi %r4, 3
+; CHECK-VEC-NEXT: lghi %r5, 4
+; CHECK-VEC-NEXT: lghi %r6, 5
+; CHECK-VEC-NEXT: vst %v0, 168(%r15), 3
+; CHECK-VEC-NEXT: mvghi 160(%r15), 6
+; CHECK-VEC-NEXT: brasl %r14, bar at PLT
+; CHECK-VEC-NEXT: lmg %r6, %r15, 248(%r15)
+; CHECK-VEC-NEXT: br %r14
;
; CHECK-STACK-LABEL: foo:
-; CHECK-STACK: aghi %r15, -200
-; CHECK-STACK-DAG: mvghi 160(%r15), 6
-; CHECK-STACK-DAG: vrepif [[REG1:%v[0-9]+]], 9
-; CHECK-STACK-DAG: vst [[REG1]], 168(%r15)
-; CHECK-STACK-DAG: vrepif [[REG2:%v[0-9]+]], 10
-; CHECK-STACK-DAG: vst [[REG2]], 184(%r15)
-; CHECK-STACK: brasl %r14, bar at PLT
+; CHECK-STACK: # %bb.0:
+; CHECK-STACK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-STACK-NEXT: .cfi_offset %r6, -112
+; CHECK-STACK-NEXT: .cfi_offset %r14, -48
+; CHECK-STACK-NEXT: .cfi_offset %r15, -40
+; CHECK-STACK-NEXT: aghi %r15, -200
+; CHECK-STACK-NEXT: .cfi_def_cfa_offset 360
+; CHECK-STACK-NEXT: vrepif %v0, 10
+; CHECK-STACK-NEXT: vst %v0, 184(%r15), 3
+; CHECK-STACK-NEXT: vrepif %v0, 9
+; CHECK-STACK-NEXT: vrepif %v24, 1
+; CHECK-STACK-NEXT: vrepif %v26, 2
+; CHECK-STACK-NEXT: vrepif %v28, 3
+; CHECK-STACK-NEXT: vrepif %v30, 4
+; CHECK-STACK-NEXT: vrepif %v25, 5
+; CHECK-STACK-NEXT: vrepif %v27, 6
+; CHECK-STACK-NEXT: vrepif %v29, 7
+; CHECK-STACK-NEXT: vrepif %v31, 8
+; CHECK-STACK-NEXT: lghi %r2, 1
+; CHECK-STACK-NEXT: lghi %r3, 2
+; CHECK-STACK-NEXT: lghi %r4, 3
+; CHECK-STACK-NEXT: lghi %r5, 4
+; CHECK-STACK-NEXT: lghi %r6, 5
+; CHECK-STACK-NEXT: vst %v0, 168(%r15), 3
+; CHECK-STACK-NEXT: mvghi 160(%r15), 6
+; CHECK-STACK-NEXT: brasl %r14, bar at PLT
+; CHECK-STACK-NEXT: lmg %r6, %r15, 248(%r15)
+; CHECK-STACK-NEXT: br %r14
call void @bar (i64 1, i64 2, i64 3, i64 4, i64 5, i64 6,
<4 x i32> <i32 1, i32 1, i32 1, i32 1>,
diff --git a/llvm/test/CodeGen/SystemZ/vec-args-02.ll b/llvm/test/CodeGen/SystemZ/vec-args-02.ll
index b6081598326af..a06daac8d7b0e 100644
--- a/llvm/test/CodeGen/SystemZ/vec-args-02.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-args-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test the handling of unnamed vector arguments.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
@@ -10,17 +11,38 @@ declare void @bar(<4 x i32>, <4 x i32>, ...)
define void @foo() {
; CHECK-VEC-LABEL: foo:
-; CHECK-VEC-DAG: vrepif %v24, 1
-; CHECK-VEC-DAG: vrepif %v26, 2
-; CHECK-VEC: brasl %r14, bar at PLT
+; CHECK-VEC: # %bb.0:
+; CHECK-VEC-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-VEC-NEXT: .cfi_offset %r14, -48
+; CHECK-VEC-NEXT: .cfi_offset %r15, -40
+; CHECK-VEC-NEXT: aghi %r15, -192
+; CHECK-VEC-NEXT: .cfi_def_cfa_offset 352
+; CHECK-VEC-NEXT: vrepif %v0, 4
+; CHECK-VEC-NEXT: vst %v0, 176(%r15), 3
+; CHECK-VEC-NEXT: vrepif %v0, 3
+; CHECK-VEC-NEXT: vrepif %v24, 1
+; CHECK-VEC-NEXT: vrepif %v26, 2
+; CHECK-VEC-NEXT: vst %v0, 160(%r15), 3
+; CHECK-VEC-NEXT: brasl %r14, bar at PLT
+; CHECK-VEC-NEXT: lmg %r14, %r15, 304(%r15)
+; CHECK-VEC-NEXT: br %r14
;
; CHECK-STACK-LABEL: foo:
-; CHECK-STACK: aghi %r15, -192
-; CHECK-STACK-DAG: vrepif [[REG1:%v[0-9]+]], 3
-; CHECK-STACK-DAG: vst [[REG1]], 160(%r15)
-; CHECK-STACK-DAG: vrepif [[REG2:%v[0-9]+]], 4
-; CHECK-STACK-DAG: vst [[REG2]], 176(%r15)
-; CHECK-STACK: brasl %r14, bar at PLT
+; CHECK-STACK: # %bb.0:
+; CHECK-STACK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-STACK-NEXT: .cfi_offset %r14, -48
+; CHECK-STACK-NEXT: .cfi_offset %r15, -40
+; CHECK-STACK-NEXT: aghi %r15, -192
+; CHECK-STACK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-STACK-NEXT: vrepif %v0, 4
+; CHECK-STACK-NEXT: vst %v0, 176(%r15), 3
+; CHECK-STACK-NEXT: vrepif %v0, 3
+; CHECK-STACK-NEXT: vrepif %v24, 1
+; CHECK-STACK-NEXT: vrepif %v26, 2
+; CHECK-STACK-NEXT: vst %v0, 160(%r15), 3
+; CHECK-STACK-NEXT: brasl %r14, bar at PLT
+; CHECK-STACK-NEXT: lmg %r14, %r15, 304(%r15)
+; CHECK-STACK-NEXT: br %r14
call void (<4 x i32>, <4 x i32>, ...) @bar
(<4 x i32> <i32 1, i32 1, i32 1, i32 1>,
diff --git a/llvm/test/CodeGen/SystemZ/vec-args-03.ll b/llvm/test/CodeGen/SystemZ/vec-args-03.ll
index c47d8461021af..0cf41a7b49f88 100644
--- a/llvm/test/CodeGen/SystemZ/vec-args-03.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-args-03.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test the handling of incoming vector arguments.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
@@ -5,12 +6,13 @@
; This routine has 10 vector arguments, which fill up %v24-%v31 and
; the two double-wide stack slots at 160 and 176.
define <4 x i32> @foo(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4,
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vl %v0, 176(%r15), 3
+; CHECK-NEXT: vsf %v24, %v26, %v0
+; CHECK-NEXT: br %r14
<4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7, <4 x i32> %v8,
<4 x i32> %v9, <4 x i32> %v10) {
-; CHECK-LABEL: foo:
-; CHECK: vl [[REG1:%v[0-9]+]], 176(%r15)
-; CHECK: vsf %v24, %v26, [[REG1]]
-; CHECK: br %r14
%y = sub <4 x i32> %v2, %v10
ret <4 x i32> %y
}
@@ -18,12 +20,13 @@ define <4 x i32> @foo(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4
; This routine has 10 vector arguments, which fill up %v24-%v31 and
; the two single-wide stack slots at 160 and 168.
define <4 x i8> @bar(<4 x i8> %v1, <4 x i8> %v2, <4 x i8> %v3, <4 x i8> %v4,
+; CHECK-LABEL: bar:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlrepg %v0, 168(%r15)
+; CHECK-NEXT: vsb %v24, %v26, %v0
+; CHECK-NEXT: br %r14
<4 x i8> %v5, <4 x i8> %v6, <4 x i8> %v7, <4 x i8> %v8,
<4 x i8> %v9, <4 x i8> %v10) {
-; CHECK-LABEL: bar:
-; CHECK: vlrepg [[REG1:%v[0-9]+]], 168(%r15)
-; CHECK: vsb %v24, %v26, [[REG1]]
-; CHECK: br %r14
%y = sub <4 x i8> %v2, %v10
ret <4 x i8> %y
}
diff --git a/llvm/test/CodeGen/SystemZ/vec-args-04.ll b/llvm/test/CodeGen/SystemZ/vec-args-04.ll
index 5176d80f08fb4..b1cd278992541 100644
--- a/llvm/test/CodeGen/SystemZ/vec-args-04.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-args-04.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test the handling of named short vector arguments.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
@@ -11,36 +12,59 @@ declare void @bar(<1 x i8>, <2 x i8>, <4 x i8>, <8 x i8>,
define void @foo() {
; CHECK-VEC-LABEL: foo:
-; CHECK-VEC-DAG: vrepib %v24, 1
-; CHECK-VEC-DAG: vrepib %v26, 2
-; CHECK-VEC-DAG: vrepib %v28, 3
-; CHECK-VEC-DAG: vrepib %v30, 4
-; CHECK-VEC-DAG: vrepib %v25, 5
-; CHECK-VEC-DAG: vrepib %v27, 6
-; CHECK-VEC-DAG: vrepib %v29, 7
-; CHECK-VEC-DAG: vrepib %v31, 8
-; CHECK-VEC: brasl %r14, bar at PLT
+; CHECK-VEC: # %bb.0:
+; CHECK-VEC-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-VEC-NEXT: .cfi_offset %r14, -48
+; CHECK-VEC-NEXT: .cfi_offset %r15, -40
+; CHECK-VEC-NEXT: aghi %r15, -192
+; CHECK-VEC-NEXT: .cfi_def_cfa_offset 352
+; CHECK-VEC-NEXT: larl %r1, .LCPI0_0
+; CHECK-VEC-NEXT: vl %v0, 0(%r1), 3
+; CHECK-VEC-NEXT: larl %r1, .LCPI0_1
+; CHECK-VEC-NEXT: vst %v0, 176(%r15), 3
+; CHECK-VEC-NEXT: vl %v0, 0(%r1), 3
+; CHECK-VEC-NEXT: vrepib %v24, 1
+; CHECK-VEC-NEXT: vrepib %v26, 2
+; CHECK-VEC-NEXT: vrepib %v28, 3
+; CHECK-VEC-NEXT: vrepib %v30, 4
+; CHECK-VEC-NEXT: vrepib %v25, 5
+; CHECK-VEC-NEXT: vrepib %v27, 6
+; CHECK-VEC-NEXT: vrepib %v29, 7
+; CHECK-VEC-NEXT: vrepib %v31, 8
+; CHECK-VEC-NEXT: vst %v0, 160(%r15), 3
+; CHECK-VEC-NEXT: brasl %r14, bar at PLT
+; CHECK-VEC-NEXT: lmg %r14, %r15, 304(%r15)
+; CHECK-VEC-NEXT: br %r14
;
+; CHECK-STACK-LABEL: foo:
+; CHECK-STACK: # %bb.0:
+; CHECK-STACK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-STACK-NEXT: .cfi_offset %r14, -48
+; CHECK-STACK-NEXT: .cfi_offset %r15, -40
+; CHECK-STACK-NEXT: aghi %r15, -192
+; CHECK-STACK-NEXT: .cfi_def_cfa_offset 352
+; CHECK-STACK-NEXT: larl %r1, .LCPI0_0
+; CHECK-STACK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-STACK-NEXT: larl %r1, .LCPI0_1
+; CHECK-STACK-NEXT: vst %v0, 176(%r15), 3
+; CHECK-STACK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-STACK-NEXT: vrepib %v24, 1
+; CHECK-STACK-NEXT: vrepib %v26, 2
+; CHECK-STACK-NEXT: vrepib %v28, 3
+; CHECK-STACK-NEXT: vrepib %v30, 4
+; CHECK-STACK-NEXT: vrepib %v25, 5
+; CHECK-STACK-NEXT: vrepib %v27, 6
+; CHECK-STACK-NEXT: vrepib %v29, 7
+; CHECK-STACK-NEXT: vrepib %v31, 8
+; CHECK-STACK-NEXT: vst %v0, 160(%r15), 3
+; CHECK-STACK-NEXT: brasl %r14, bar at PLT
+; CHECK-STACK-NEXT: lmg %r14, %r15, 304(%r15)
+; CHECK-STACK-NEXT: br %r14
-; CHECK-STACK: .LCPI0_0:
-; CHECK-STACK: .quad 795741901033570304 # 0xb0b0b0b00000000
-; CHECK-STACK: .quad 868082074056920076 # 0xc0c0c0c0c0c0c0c
-; CHECK-STACK: .LCPI0_1:
-; CHECK-STACK: .quad 648518346341351424 # 0x900000000000000
-; CHECK-STACK: .quad 723390690146385920 # 0xa0a000000000000
-; CHECK-STACK-LABEL: foo:
-; CHECK-STACK: aghi %r15, -192
-; CHECK-STACK-DAG: larl [[REG1:%r[0-9]+]], .LCPI0_0
-; CHECK-STACK-DAG: vl [[VREG0:%v[0-9]+]], 0([[REG1]])
-; CHECK-STACK-DAG: vst [[VREG0]], 176(%r15)
-; CHECK-STACK-DAG: larl [[REG2:%r[0-9]+]], .LCPI0_1
-; CHECK-STACK-DAG: vl [[VREG1:%v[0-9]+]], 0([[REG2]])
-; CHECK-STACK-DAG: vst [[VREG1]], 160(%r15)
-; CHECK-STACK: brasl %r14, bar at PLT
call void @bar (<1 x i8> <i8 1>,
<2 x i8> <i8 2, i8 2>,
diff --git a/llvm/test/CodeGen/SystemZ/vec-args-05.ll b/llvm/test/CodeGen/SystemZ/vec-args-05.ll
index 8c5ff84142921..86348248d72eb 100644
--- a/llvm/test/CodeGen/SystemZ/vec-args-05.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-args-05.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test the handling of unnamed short vector arguments.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
@@ -10,19 +11,36 @@ declare void @bar(<4 x i8>, <4 x i8>, ...)
define void @foo() {
; CHECK-VEC-LABEL: foo:
-; CHECK-VEC-DAG: vrepib %v24, 1
-; CHECK-VEC-DAG: vrepib %v26, 2
-; CHECK-VEC: brasl %r14, bar at PLT
+; CHECK-VEC: # %bb.0:
+; CHECK-VEC-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-VEC-NEXT: .cfi_offset %r14, -48
+; CHECK-VEC-NEXT: .cfi_offset %r15, -40
+; CHECK-VEC-NEXT: aghi %r15, -176
+; CHECK-VEC-NEXT: .cfi_def_cfa_offset 336
+; CHECK-VEC-NEXT: larl %r1, .LCPI0_0
+; CHECK-VEC-NEXT: vl %v0, 0(%r1), 3
+; CHECK-VEC-NEXT: vrepib %v24, 1
+; CHECK-VEC-NEXT: vrepib %v26, 2
+; CHECK-VEC-NEXT: vst %v0, 160(%r15), 3
+; CHECK-VEC-NEXT: brasl %r14, bar at PLT
+; CHECK-VEC-NEXT: lmg %r14, %r15, 288(%r15)
+; CHECK-VEC-NEXT: br %r14
;
-; CHECK-STACK: .LCPI0_0:
-; CHECK-STACK: .quad 217020518463700992 # 0x303030300000000
-; CHECK-STACK: .quad 289360691284934656 # 0x404040400000000
; CHECK-STACK-LABEL: foo:
-; CHECK-STACK: aghi %r15, -176
-; CHECK-STACK-DAG: larl [[REG1:%r[0-9]+]], .LCPI0_0
-; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]])
-; CHECK-STACK-DAG: vst [[VREG]], 160(%r15)
-; CHECK-STACK: brasl %r14, bar at PLT
+; CHECK-STACK: # %bb.0:
+; CHECK-STACK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-STACK-NEXT: .cfi_offset %r14, -48
+; CHECK-STACK-NEXT: .cfi_offset %r15, -40
+; CHECK-STACK-NEXT: aghi %r15, -176
+; CHECK-STACK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-STACK-NEXT: larl %r1, .LCPI0_0
+; CHECK-STACK-NEXT: vl %v0, 0(%r1), 3
+; CHECK-STACK-NEXT: vrepib %v24, 1
+; CHECK-STACK-NEXT: vrepib %v26, 2
+; CHECK-STACK-NEXT: vst %v0, 160(%r15), 3
+; CHECK-STACK-NEXT: brasl %r14, bar at PLT
+; CHECK-STACK-NEXT: lmg %r14, %r15, 288(%r15)
+; CHECK-STACK-NEXT: br %r14
call void (<4 x i8>, <4 x i8>, ...) @bar
(<4 x i8> <i8 1, i8 1, i8 1, i8 1>,
diff --git a/llvm/test/CodeGen/SystemZ/vec-args-07.ll b/llvm/test/CodeGen/SystemZ/vec-args-07.ll
index 57dda578f2715..b8e51b1e70825 100644
--- a/llvm/test/CodeGen/SystemZ/vec-args-07.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-args-07.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test calling functions with multiple return values (LLVM ABI extension)
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
@@ -10,17 +11,31 @@ declare { <2 x double>, <2 x double>, <2 x double>, <2 x double>,
define <2 x double> @f1() {
; CHECK-LABEL: f1:
-; CHECK: brasl %r14, bar1
-; CHECK: vlr %v24, %v31
-; CHECK: br %r14
-
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -160
+; CHECK-NEXT: .cfi_def_cfa_offset 320
+; CHECK-NEXT: brasl %r14, bar1 at PLT
+; CHECK-NEXT: vlr %v24, %v31
+; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
+; CHECK-NEXT: br %r14
+;
; SOFT-FLOAT-LABEL: f1:
-; SOFT-FLOAT-NOT: %{{[fv]}}
-; SOFT-FLOAT: brasl %r14, bar1
-; SOFT-FLOAT-NEXT: lg %r3, 280(%r15)
-; SOFT-FLOAT-NEXT: lg %r2, 272(%r15)
-; SOFT-FLOAT-NEXT: lmg %r14, %r15, 400(%r15)
-; SOFT-FLOAT-NEXT: br %r14
+; SOFT-FLOAT: # %bb.0:
+; SOFT-FLOAT-NEXT: stmg %r14, %r15, 112(%r15)
+; SOFT-FLOAT-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-NEXT: aghi %r15, -288
+; SOFT-FLOAT-NEXT: .cfi_def_cfa_offset 448
+; SOFT-FLOAT-NEXT: la %r2, 160(%r15)
+; SOFT-FLOAT-NEXT: brasl %r14, bar1 at PLT
+; SOFT-FLOAT-NEXT: lg %r3, 280(%r15)
+; SOFT-FLOAT-NEXT: lg %r2, 272(%r15)
+; SOFT-FLOAT-NEXT: lmg %r14, %r15, 400(%r15)
+; SOFT-FLOAT-NEXT: br %r14
+
%mret = call { <2 x double>, <2 x double>,
<2 x double>, <2 x double>,
<2 x double>, <2 x double>,
@@ -39,18 +54,32 @@ declare { <2 x double>, <2 x double>, <2 x double>, <2 x double>,
define <2 x double> @f2() {
; CHECK-LABEL: f2:
-; CHECK: la %r2, 160(%r15)
-; CHECK: brasl %r14, bar2
-; CHECK: vl %v24, 288(%r15)
-; CHECK: br %r14
-
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -304
+; CHECK-NEXT: .cfi_def_cfa_offset 464
+; CHECK-NEXT: la %r2, 160(%r15)
+; CHECK-NEXT: brasl %r14, bar2 at PLT
+; CHECK-NEXT: vl %v24, 288(%r15), 3
+; CHECK-NEXT: lmg %r14, %r15, 416(%r15)
+; CHECK-NEXT: br %r14
+;
; SOFT-FLOAT-LABEL: f2:
-; SOFT-FLOAT-NOT: %{{[fv]}}
-; SOFT-FLOAT: brasl %r14, bar2
-; SOFT-FLOAT-NEXT: lg %r3, 296(%r15)
-; SOFT-FLOAT-NEXT: lg %r2, 288(%r15)
-; SOFT-FLOAT-NEXT: lmg %r14, %r15, 416(%r15)
-; SOFT-FLOAT-NEXT: br %r14
+; SOFT-FLOAT: # %bb.0:
+; SOFT-FLOAT-NEXT: stmg %r14, %r15, 112(%r15)
+; SOFT-FLOAT-NEXT: .cfi_offset %r14, -48
+; SOFT-FLOAT-NEXT: .cfi_offset %r15, -40
+; SOFT-FLOAT-NEXT: aghi %r15, -304
+; SOFT-FLOAT-NEXT: .cfi_def_cfa_offset 464
+; SOFT-FLOAT-NEXT: la %r2, 160(%r15)
+; SOFT-FLOAT-NEXT: brasl %r14, bar2 at PLT
+; SOFT-FLOAT-NEXT: lg %r3, 296(%r15)
+; SOFT-FLOAT-NEXT: lg %r2, 288(%r15)
+; SOFT-FLOAT-NEXT: lmg %r14, %r15, 416(%r15)
+; SOFT-FLOAT-NEXT: br %r14
+
%mret = call { <2 x double>, <2 x double>,
<2 x double>, <2 x double>,
<2 x double>, <2 x double>,
diff --git a/llvm/test/CodeGen/SystemZ/vec-bswap-01.ll b/llvm/test/CodeGen/SystemZ/vec-bswap-01.ll
index 22c9c52316323..d7fdb79daa278 100644
--- a/llvm/test/CodeGen/SystemZ/vec-bswap-01.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-bswap-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test loads of byte-swapped vector elements.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
@@ -9,8 +10,9 @@ declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
; Test v8i16 loads.
define <8 x i16> @f1(ptr %ptr) {
; CHECK-LABEL: f1:
-; CHECK: vlbrh %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrh %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%load = load <8 x i16>, ptr %ptr
%ret = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %load)
ret <8 x i16> %ret
@@ -19,8 +21,9 @@ define <8 x i16> @f1(ptr %ptr) {
; Test v4i32 loads.
define <4 x i32> @f2(ptr %ptr) {
; CHECK-LABEL: f2:
-; CHECK: vlbrf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%load = load <4 x i32>, ptr %ptr
%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)
ret <4 x i32> %ret
@@ -29,8 +32,9 @@ define <4 x i32> @f2(ptr %ptr) {
; Test v2i64 loads.
define <2 x i64> @f3(ptr %ptr) {
; CHECK-LABEL: f3:
-; CHECK: vlbrg %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%load = load <2 x i64>, ptr %ptr
%ret = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %load)
ret <2 x i64> %ret
@@ -39,8 +43,9 @@ define <2 x i64> @f3(ptr %ptr) {
; Test the highest aligned in-range offset.
define <4 x i32> @f4(ptr %base) {
; CHECK-LABEL: f4:
-; CHECK: vlbrf %v24, 4080(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrf %v24, 4080(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr <4 x i32>, ptr %base, i64 255
%load = load <4 x i32>, ptr %ptr
%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)
@@ -50,8 +55,9 @@ define <4 x i32> @f4(ptr %base) {
; Test the highest unaligned in-range offset.
define <4 x i32> @f5(ptr %base) {
; CHECK-LABEL: f5:
-; CHECK: vlbrf %v24, 4095(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrf %v24, 4095(%r2)
+; CHECK-NEXT: br %r14
%addr = getelementptr i8, ptr %base, i64 4095
%load = load <4 x i32>, ptr %addr
%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)
@@ -61,9 +67,10 @@ define <4 x i32> @f5(ptr %base) {
; Test the next offset up, which requires separate address logic,
define <4 x i32> @f6(ptr %base) {
; CHECK-LABEL: f6:
-; CHECK: aghi %r2, 4096
-; CHECK: vlbrf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlbrf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr <4 x i32>, ptr %base, i64 256
%load = load <4 x i32>, ptr %ptr
%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)
@@ -73,9 +80,10 @@ define <4 x i32> @f6(ptr %base) {
; Test negative offsets, which also require separate address logic,
define <4 x i32> @f7(ptr %base) {
; CHECK-LABEL: f7:
-; CHECK: aghi %r2, -16
-; CHECK: vlbrf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, -16
+; CHECK-NEXT: vlbrf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr <4 x i32>, ptr %base, i64 -1
%load = load <4 x i32>, ptr %ptr
%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)
@@ -85,8 +93,9 @@ define <4 x i32> @f7(ptr %base) {
; Check that indexes are allowed.
define <4 x i32> @f8(ptr %base, i64 %index) {
; CHECK-LABEL: f8:
-; CHECK: vlbrf %v24, 0(%r3,%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrf %v24, 0(%r3,%r2)
+; CHECK-NEXT: br %r14
%addr = getelementptr i8, ptr %base, i64 %index
%load = load <4 x i32>, ptr %addr
%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)
diff --git a/llvm/test/CodeGen/SystemZ/vec-bswap-02.ll b/llvm/test/CodeGen/SystemZ/vec-bswap-02.ll
index b210aa8304ba2..344a38bea844f 100644
--- a/llvm/test/CodeGen/SystemZ/vec-bswap-02.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-bswap-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test stores of byte-swapped vector elements.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
@@ -9,8 +10,9 @@ declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
; Test v8i16 stores.
define void @f1(<8 x i16> %val, ptr %ptr) {
; CHECK-LABEL: f1:
-; CHECK: vstbrh %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstbrh %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%swap = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %val)
store <8 x i16> %swap, ptr %ptr
ret void
@@ -19,8 +21,9 @@ define void @f1(<8 x i16> %val, ptr %ptr) {
; Test v4i32 stores.
define void @f2(<4 x i32> %val, ptr %ptr) {
; CHECK-LABEL: f2:
-; CHECK: vstbrf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstbrf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
store <4 x i32> %swap, ptr %ptr
ret void
@@ -29,8 +32,9 @@ define void @f2(<4 x i32> %val, ptr %ptr) {
; Test v2i64 stores.
define void @f3(<2 x i64> %val, ptr %ptr) {
; CHECK-LABEL: f3:
-; CHECK: vstbrg %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstbrg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%swap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val)
store <2 x i64> %swap, ptr %ptr
ret void
@@ -39,8 +43,9 @@ define void @f3(<2 x i64> %val, ptr %ptr) {
; Test the highest aligned in-range offset.
define void @f4(<4 x i32> %val, ptr %base) {
; CHECK-LABEL: f4:
-; CHECK: vstbrf %v24, 4080(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstbrf %v24, 4080(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr <4 x i32>, ptr %base, i64 255
%swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
store <4 x i32> %swap, ptr %ptr
@@ -50,8 +55,9 @@ define void @f4(<4 x i32> %val, ptr %base) {
; Test the highest unaligned in-range offset.
define void @f5(<4 x i32> %val, ptr %base) {
; CHECK-LABEL: f5:
-; CHECK: vstbrf %v24, 4095(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstbrf %v24, 4095(%r2)
+; CHECK-NEXT: br %r14
%addr = getelementptr i8, ptr %base, i64 4095
%swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
store <4 x i32> %swap, ptr %addr, align 1
@@ -61,9 +67,10 @@ define void @f5(<4 x i32> %val, ptr %base) {
; Test the next offset up, which requires separate address logic,
define void @f6(<4 x i32> %val, ptr %base) {
; CHECK-LABEL: f6:
-; CHECK: aghi %r2, 4096
-; CHECK: vstbrf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vstbrf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr <4 x i32>, ptr %base, i64 256
%swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
store <4 x i32> %swap, ptr %ptr
@@ -73,9 +80,10 @@ define void @f6(<4 x i32> %val, ptr %base) {
; Test negative offsets, which also require separate address logic,
define void @f7(<4 x i32> %val, ptr %base) {
; CHECK-LABEL: f7:
-; CHECK: aghi %r2, -16
-; CHECK: vstbrf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, -16
+; CHECK-NEXT: vstbrf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr <4 x i32>, ptr %base, i64 -1
%swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
store <4 x i32> %swap, ptr %ptr
@@ -85,8 +93,9 @@ define void @f7(<4 x i32> %val, ptr %base) {
; Check that indexes are allowed.
define void @f8(<4 x i32> %val, ptr %base, i64 %index) {
; CHECK-LABEL: f8:
-; CHECK: vstbrf %v24, 0(%r3,%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstbrf %v24, 0(%r3,%r2)
+; CHECK-NEXT: br %r14
%addr = getelementptr i8, ptr %base, i64 %index
%swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
store <4 x i32> %swap, ptr %addr, align 1
diff --git a/llvm/test/CodeGen/SystemZ/vec-bswap-03.ll b/llvm/test/CodeGen/SystemZ/vec-bswap-03.ll
index eb7fbf6ac0c51..beb87faa0fd79 100644
--- a/llvm/test/CodeGen/SystemZ/vec-bswap-03.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-bswap-03.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test vector insertion of byte-swapped memory values.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
@@ -12,8 +13,9 @@ declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
; Test v8i16 insertion into the first element.
define <8 x i16> @f1(<8 x i16> %val, ptr %ptr) {
; CHECK-LABEL: f1:
-; CHECK: vlebrh %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrh %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%element = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %element)
%ret = insertelement <8 x i16> %val, i16 %swap, i32 0
@@ -23,8 +25,9 @@ define <8 x i16> @f1(<8 x i16> %val, ptr %ptr) {
; Test v8i16 insertion into the last element.
define <8 x i16> @f2(<8 x i16> %val, ptr %ptr) {
; CHECK-LABEL: f2:
-; CHECK: vlebrh %v24, 0(%r2), 7
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrh %v24, 0(%r2), 7
+; CHECK-NEXT: br %r14
%element = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %element)
%ret = insertelement <8 x i16> %val, i16 %swap, i32 7
@@ -34,8 +37,9 @@ define <8 x i16> @f2(<8 x i16> %val, ptr %ptr) {
; Test v8i16 insertion with the highest in-range offset.
define <8 x i16> @f3(<8 x i16> %val, ptr %base) {
; CHECK-LABEL: f3:
-; CHECK: vlebrh %v24, 4094(%r2), 5
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrh %v24, 4094(%r2), 5
+; CHECK-NEXT: br %r14
%ptr = getelementptr i16, ptr %base, i32 2047
%element = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %element)
@@ -46,9 +50,10 @@ define <8 x i16> @f3(<8 x i16> %val, ptr %base) {
; Test v8i16 insertion with the first ouf-of-range offset.
define <8 x i16> @f4(<8 x i16> %val, ptr %base) {
; CHECK-LABEL: f4:
-; CHECK: aghi %r2, 4096
-; CHECK: vlebrh %v24, 0(%r2), 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlebrh %v24, 0(%r2), 1
+; CHECK-NEXT: br %r14
%ptr = getelementptr i16, ptr %base, i32 2048
%element = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %element)
@@ -59,8 +64,10 @@ define <8 x i16> @f4(<8 x i16> %val, ptr %base) {
; Test v8i16 insertion into a variable element.
define <8 x i16> @f5(<8 x i16> %val, ptr %ptr, i32 %index) {
; CHECK-LABEL: f5:
-; CHECK-NOT: vlebrh
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lrvh %r0, 0(%r2)
+; CHECK-NEXT: vlvgh %v24, %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%element = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %element)
%ret = insertelement <8 x i16> %val, i16 %swap, i32 %index
@@ -70,8 +77,9 @@ define <8 x i16> @f5(<8 x i16> %val, ptr %ptr, i32 %index) {
; Test v8i16 insertion using a pair of vector bswaps.
define <8 x i16> @f6(<8 x i16> %val, ptr %ptr) {
; CHECK-LABEL: f6:
-; CHECK: vlebrh %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrh %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%element = load i16, ptr %ptr
%swapval = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %val)
%insert = insertelement <8 x i16> %swapval, i16 %element, i32 0
@@ -82,8 +90,9 @@ define <8 x i16> @f6(<8 x i16> %val, ptr %ptr) {
; Test v4i32 insertion into the first element.
define <4 x i32> @f7(<4 x i32> %val, ptr %ptr) {
; CHECK-LABEL: f7:
-; CHECK: vlebrf %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrf %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%element = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %element)
%ret = insertelement <4 x i32> %val, i32 %swap, i32 0
@@ -93,8 +102,9 @@ define <4 x i32> @f7(<4 x i32> %val, ptr %ptr) {
; Test v4i32 insertion into the last element.
define <4 x i32> @f8(<4 x i32> %val, ptr %ptr) {
; CHECK-LABEL: f8:
-; CHECK: vlebrf %v24, 0(%r2), 3
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrf %v24, 0(%r2), 3
+; CHECK-NEXT: br %r14
%element = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %element)
%ret = insertelement <4 x i32> %val, i32 %swap, i32 3
@@ -104,8 +114,9 @@ define <4 x i32> @f8(<4 x i32> %val, ptr %ptr) {
; Test v4i32 insertion with the highest in-range offset.
define <4 x i32> @f9(<4 x i32> %val, ptr %base) {
; CHECK-LABEL: f9:
-; CHECK: vlebrf %v24, 4092(%r2), 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrf %v24, 4092(%r2), 2
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %base, i32 1023
%element = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %element)
@@ -116,9 +127,10 @@ define <4 x i32> @f9(<4 x i32> %val, ptr %base) {
; Test v4i32 insertion with the first ouf-of-range offset.
define <4 x i32> @f10(<4 x i32> %val, ptr %base) {
; CHECK-LABEL: f10:
-; CHECK: aghi %r2, 4096
-; CHECK: vlebrf %v24, 0(%r2), 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlebrf %v24, 0(%r2), 1
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %base, i32 1024
%element = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %element)
@@ -129,8 +141,10 @@ define <4 x i32> @f10(<4 x i32> %val, ptr %base) {
; Test v4i32 insertion into a variable element.
define <4 x i32> @f11(<4 x i32> %val, ptr %ptr, i32 %index) {
; CHECK-LABEL: f11:
-; CHECK-NOT: vlebrf
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lrv %r0, 0(%r2)
+; CHECK-NEXT: vlvgf %v24, %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%element = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %element)
%ret = insertelement <4 x i32> %val, i32 %swap, i32 %index
@@ -140,8 +154,9 @@ define <4 x i32> @f11(<4 x i32> %val, ptr %ptr, i32 %index) {
; Test v4i32 insertion using a pair of vector bswaps.
define <4 x i32> @f12(<4 x i32> %val, ptr %ptr) {
; CHECK-LABEL: f12:
-; CHECK: vlebrf %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrf %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%element = load i32, ptr %ptr
%swapval = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
%insert = insertelement <4 x i32> %swapval, i32 %element, i32 0
@@ -152,8 +167,9 @@ define <4 x i32> @f12(<4 x i32> %val, ptr %ptr) {
; Test v2i64 insertion into the first element.
define <2 x i64> @f13(<2 x i64> %val, ptr %ptr) {
; CHECK-LABEL: f13:
-; CHECK: vlebrg %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrg %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%element = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %element)
%ret = insertelement <2 x i64> %val, i64 %swap, i32 0
@@ -163,8 +179,9 @@ define <2 x i64> @f13(<2 x i64> %val, ptr %ptr) {
; Test v2i64 insertion into the last element.
define <2 x i64> @f14(<2 x i64> %val, ptr %ptr) {
; CHECK-LABEL: f14:
-; CHECK: vlebrg %v24, 0(%r2), 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrg %v24, 0(%r2), 1
+; CHECK-NEXT: br %r14
%element = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %element)
%ret = insertelement <2 x i64> %val, i64 %swap, i32 1
@@ -174,8 +191,9 @@ define <2 x i64> @f14(<2 x i64> %val, ptr %ptr) {
; Test v2i64 insertion with the highest in-range offset.
define <2 x i64> @f15(<2 x i64> %val, ptr %base) {
; CHECK-LABEL: f15:
-; CHECK: vlebrg %v24, 4088(%r2), 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrg %v24, 4088(%r2), 1
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %base, i32 511
%element = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %element)
@@ -186,9 +204,10 @@ define <2 x i64> @f15(<2 x i64> %val, ptr %base) {
; Test v2i64 insertion with the first ouf-of-range offset.
define <2 x i64> @f16(<2 x i64> %val, ptr %base) {
; CHECK-LABEL: f16:
-; CHECK: aghi %r2, 4096
-; CHECK: vlebrg %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlebrg %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %base, i32 512
%element = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %element)
@@ -199,8 +218,10 @@ define <2 x i64> @f16(<2 x i64> %val, ptr %base) {
; Test v2i64 insertion into a variable element.
define <2 x i64> @f17(<2 x i64> %val, ptr %ptr, i32 %index) {
; CHECK-LABEL: f17:
-; CHECK-NOT: vlebrg
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lrvg %r0, 0(%r2)
+; CHECK-NEXT: vlvgg %v24, %r0, 0(%r3)
+; CHECK-NEXT: br %r14
%element = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %element)
%ret = insertelement <2 x i64> %val, i64 %swap, i32 %index
@@ -210,8 +231,9 @@ define <2 x i64> @f17(<2 x i64> %val, ptr %ptr, i32 %index) {
; Test v2i64 insertion using a pair of vector bswaps.
define <2 x i64> @f18(<2 x i64> %val, ptr %ptr) {
; CHECK-LABEL: f18:
-; CHECK: vlebrg %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlebrg %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%element = load i64, ptr %ptr
%swapval = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val)
%insert = insertelement <2 x i64> %swapval, i64 %element, i32 0
diff --git a/llvm/test/CodeGen/SystemZ/vec-bswap-04.ll b/llvm/test/CodeGen/SystemZ/vec-bswap-04.ll
index 90fe2991218d0..bf500a7148a56 100644
--- a/llvm/test/CodeGen/SystemZ/vec-bswap-04.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-bswap-04.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test vector extraction of byte-swapped value to memory.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
@@ -12,8 +13,9 @@ declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
; Test v8i16 extraction from the first element.
define void @f1(<8 x i16> %val, ptr %ptr) {
; CHECK-LABEL: f1:
-; CHECK: vstebrh %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrh %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%element = extractelement <8 x i16> %val, i32 0
%swap = call i16 @llvm.bswap.i16(i16 %element)
store i16 %swap, ptr %ptr
@@ -23,8 +25,9 @@ define void @f1(<8 x i16> %val, ptr %ptr) {
; Test v8i16 extraction from the last element.
define void @f2(<8 x i16> %val, ptr %ptr) {
; CHECK-LABEL: f2:
-; CHECK: vstebrh %v24, 0(%r2), 7
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrh %v24, 0(%r2), 7
+; CHECK-NEXT: br %r14
%element = extractelement <8 x i16> %val, i32 7
%swap = call i16 @llvm.bswap.i16(i16 %element)
store i16 %swap, ptr %ptr
@@ -35,8 +38,8 @@ define void @f2(<8 x i16> %val, ptr %ptr) {
; but we don't care what it does.
define void @f3(<8 x i16> %val, ptr %ptr) {
; CHECK-LABEL: f3:
-; CHECK-NOT: vstebrh %v24, 0(%r2), 8
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: br %r14
%element = extractelement <8 x i16> %val, i32 8
%swap = call i16 @llvm.bswap.i16(i16 %element)
store i16 %swap, ptr %ptr
@@ -46,8 +49,9 @@ define void @f3(<8 x i16> %val, ptr %ptr) {
; Test v8i16 extraction with the highest in-range offset.
define void @f4(<8 x i16> %val, ptr %base) {
; CHECK-LABEL: f4:
-; CHECK: vstebrh %v24, 4094(%r2), 5
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrh %v24, 4094(%r2), 5
+; CHECK-NEXT: br %r14
%ptr = getelementptr i16, ptr %base, i32 2047
%element = extractelement <8 x i16> %val, i32 5
%swap = call i16 @llvm.bswap.i16(i16 %element)
@@ -58,9 +62,10 @@ define void @f4(<8 x i16> %val, ptr %base) {
; Test v8i16 extraction with the first ouf-of-range offset.
define void @f5(<8 x i16> %val, ptr %base) {
; CHECK-LABEL: f5:
-; CHECK: aghi %r2, 4096
-; CHECK: vstebrh %v24, 0(%r2), 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vstebrh %v24, 0(%r2), 1
+; CHECK-NEXT: br %r14
%ptr = getelementptr i16, ptr %base, i32 2048
%element = extractelement <8 x i16> %val, i32 1
%swap = call i16 @llvm.bswap.i16(i16 %element)
@@ -71,8 +76,10 @@ define void @f5(<8 x i16> %val, ptr %base) {
; Test v8i16 extraction from a variable element.
define void @f6(<8 x i16> %val, ptr %ptr, i32 %index) {
; CHECK-LABEL: f6:
-; CHECK-NOT: vstebrh
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlgvh %r0, %v24, 0(%r3)
+; CHECK-NEXT: strvh %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%element = extractelement <8 x i16> %val, i32 %index
%swap = call i16 @llvm.bswap.i16(i16 %element)
store i16 %swap, ptr %ptr
@@ -82,8 +89,9 @@ define void @f6(<8 x i16> %val, ptr %ptr, i32 %index) {
; Test v8i16 extraction using a vector bswap.
define void @f7(<8 x i16> %val, ptr %ptr) {
; CHECK-LABEL: f7:
-; CHECK: vstebrh %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrh %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%swap = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %val)
%element = extractelement <8 x i16> %swap, i32 0
store i16 %element, ptr %ptr
@@ -93,8 +101,9 @@ define void @f7(<8 x i16> %val, ptr %ptr) {
; Test v4i32 extraction from the first element.
define void @f8(<4 x i32> %val, ptr %ptr) {
; CHECK-LABEL: f8:
-; CHECK: vstebrf %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrf %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%element = extractelement <4 x i32> %val, i32 0
%swap = call i32 @llvm.bswap.i32(i32 %element)
store i32 %swap, ptr %ptr
@@ -104,8 +113,9 @@ define void @f8(<4 x i32> %val, ptr %ptr) {
; Test v4i32 extraction from the last element.
define void @f9(<4 x i32> %val, ptr %ptr) {
; CHECK-LABEL: f9:
-; CHECK: vstebrf %v24, 0(%r2), 3
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrf %v24, 0(%r2), 3
+; CHECK-NEXT: br %r14
%element = extractelement <4 x i32> %val, i32 3
%swap = call i32 @llvm.bswap.i32(i32 %element)
store i32 %swap, ptr %ptr
@@ -116,8 +126,8 @@ define void @f9(<4 x i32> %val, ptr %ptr) {
; but we don't care what it does.
define void @f10(<4 x i32> %val, ptr %ptr) {
; CHECK-LABEL: f10:
-; CHECK-NOT: vstebrf %v24, 0(%r2), 4
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: br %r14
%element = extractelement <4 x i32> %val, i32 4
%swap = call i32 @llvm.bswap.i32(i32 %element)
store i32 %swap, ptr %ptr
@@ -127,8 +137,9 @@ define void @f10(<4 x i32> %val, ptr %ptr) {
; Test v4i32 extraction with the highest in-range offset.
define void @f11(<4 x i32> %val, ptr %base) {
; CHECK-LABEL: f11:
-; CHECK: vstebrf %v24, 4092(%r2), 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrf %v24, 4092(%r2), 2
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %base, i32 1023
%element = extractelement <4 x i32> %val, i32 2
%swap = call i32 @llvm.bswap.i32(i32 %element)
@@ -139,9 +150,10 @@ define void @f11(<4 x i32> %val, ptr %base) {
; Test v4i32 extraction with the first ouf-of-range offset.
define void @f12(<4 x i32> %val, ptr %base) {
; CHECK-LABEL: f12:
-; CHECK: aghi %r2, 4096
-; CHECK: vstebrf %v24, 0(%r2), 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vstebrf %v24, 0(%r2), 1
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %base, i32 1024
%element = extractelement <4 x i32> %val, i32 1
%swap = call i32 @llvm.bswap.i32(i32 %element)
@@ -152,8 +164,10 @@ define void @f12(<4 x i32> %val, ptr %base) {
; Test v4i32 extraction from a variable element.
define void @f13(<4 x i32> %val, ptr %ptr, i32 %index) {
; CHECK-LABEL: f13:
-; CHECK-NOT: vstebrf
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlgvf %r0, %v24, 0(%r3)
+; CHECK-NEXT: strv %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%element = extractelement <4 x i32> %val, i32 %index
%swap = call i32 @llvm.bswap.i32(i32 %element)
store i32 %swap, ptr %ptr
@@ -163,8 +177,9 @@ define void @f13(<4 x i32> %val, ptr %ptr, i32 %index) {
; Test v4i32 extraction using a vector bswap.
define void @f14(<4 x i32> %val, ptr %ptr) {
; CHECK-LABEL: f14:
-; CHECK: vstebrf %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrf %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
%element = extractelement <4 x i32> %swap, i32 0
store i32 %element, ptr %ptr
@@ -174,8 +189,9 @@ define void @f14(<4 x i32> %val, ptr %ptr) {
; Test v2i64 extraction from the first element.
define void @f15(<2 x i64> %val, ptr %ptr) {
; CHECK-LABEL: f15:
-; CHECK: vstebrg %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrg %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%element = extractelement <2 x i64> %val, i32 0
%swap = call i64 @llvm.bswap.i64(i64 %element)
store i64 %swap, ptr %ptr
@@ -185,8 +201,9 @@ define void @f15(<2 x i64> %val, ptr %ptr) {
; Test v2i64 extraction from the last element.
define void @f16(<2 x i64> %val, ptr %ptr) {
; CHECK-LABEL: f16:
-; CHECK: vstebrg %v24, 0(%r2), 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrg %v24, 0(%r2), 1
+; CHECK-NEXT: br %r14
%element = extractelement <2 x i64> %val, i32 1
%swap = call i64 @llvm.bswap.i64(i64 %element)
store i64 %swap, ptr %ptr
@@ -197,8 +214,8 @@ define void @f16(<2 x i64> %val, ptr %ptr) {
; but we don't care what it does.
define void @f17(<2 x i64> %val, ptr %ptr) {
; CHECK-LABEL: f17:
-; CHECK-NOT: vstebrg %v24, 0(%r2), 2
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: br %r14
%element = extractelement <2 x i64> %val, i32 2
%swap = call i64 @llvm.bswap.i64(i64 %element)
store i64 %swap, ptr %ptr
@@ -208,8 +225,9 @@ define void @f17(<2 x i64> %val, ptr %ptr) {
; Test v2i64 extraction with the highest in-range offset.
define void @f18(<2 x i64> %val, ptr %base) {
; CHECK-LABEL: f18:
-; CHECK: vstebrg %v24, 4088(%r2), 1
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrg %v24, 4088(%r2), 1
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %base, i32 511
%element = extractelement <2 x i64> %val, i32 1
%swap = call i64 @llvm.bswap.i64(i64 %element)
@@ -220,9 +238,10 @@ define void @f18(<2 x i64> %val, ptr %base) {
; Test v2i64 extraction with the first ouf-of-range offset.
define void @f19(<2 x i64> %val, ptr %base) {
; CHECK-LABEL: f19:
-; CHECK: aghi %r2, 4096
-; CHECK: vstebrg %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vstebrg %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %base, i32 512
%element = extractelement <2 x i64> %val, i32 0
%swap = call i64 @llvm.bswap.i64(i64 %element)
@@ -233,8 +252,10 @@ define void @f19(<2 x i64> %val, ptr %base) {
; Test v2i64 extraction from a variable element.
define void @f20(<2 x i64> %val, ptr %ptr, i32 %index) {
; CHECK-LABEL: f20:
-; CHECK-NOT: vstebrg
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlgvg %r0, %v24, 0(%r3)
+; CHECK-NEXT: strvg %r0, 0(%r2)
+; CHECK-NEXT: br %r14
%element = extractelement <2 x i64> %val, i32 %index
%swap = call i64 @llvm.bswap.i64(i64 %element)
store i64 %swap, ptr %ptr
@@ -244,8 +265,9 @@ define void @f20(<2 x i64> %val, ptr %ptr, i32 %index) {
; Test v2i64 extraction using a vector bswap.
define void @f21(<2 x i64> %val, ptr %ptr) {
; CHECK-LABEL: f21:
-; CHECK: vstebrg %v24, 0(%r2), 0
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vstebrg %v24, 0(%r2), 0
+; CHECK-NEXT: br %r14
%swap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val)
%element = extractelement <2 x i64> %swap, i32 0
store i64 %element, ptr %ptr
diff --git a/llvm/test/CodeGen/SystemZ/vec-bswap-05.ll b/llvm/test/CodeGen/SystemZ/vec-bswap-05.ll
index 398e8160b6c90..f26e28fa7d99c 100644
--- a/llvm/test/CodeGen/SystemZ/vec-bswap-05.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-bswap-05.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test vector insertions of byte-swapped memory values into 0.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
@@ -12,8 +13,9 @@ declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
; Test VLLEBRZH.
define <8 x i16> @f1(ptr %ptr) {
; CHECK-LABEL: f1:
-; CHECK: vllebrzh %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vllebrzh %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %val)
%ret = insertelement <8 x i16> zeroinitializer, i16 %swap, i32 3
@@ -23,8 +25,9 @@ define <8 x i16> @f1(ptr %ptr) {
; Test VLLEBRZH using a vector bswap.
define <8 x i16> @f2(ptr %ptr) {
; CHECK-LABEL: f2:
-; CHECK: vllebrzh %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vllebrzh %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i16, ptr %ptr
%insert = insertelement <8 x i16> zeroinitializer, i16 %val, i32 3
%ret = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %insert)
@@ -34,8 +37,9 @@ define <8 x i16> @f2(ptr %ptr) {
; Test VLLEBRZF.
define <4 x i32> @f3(ptr %ptr) {
; CHECK-LABEL: f3:
-; CHECK: vllebrzf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vllebrzf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %val)
%ret = insertelement <4 x i32> zeroinitializer, i32 %swap, i32 1
@@ -45,8 +49,9 @@ define <4 x i32> @f3(ptr %ptr) {
; Test VLLEBRZF using a vector bswap.
define <4 x i32> @f4(ptr %ptr) {
; CHECK-LABEL: f4:
-; CHECK: vllebrzf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vllebrzf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i32, ptr %ptr
%insert = insertelement <4 x i32> zeroinitializer, i32 %val, i32 1
%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %insert)
@@ -56,8 +61,9 @@ define <4 x i32> @f4(ptr %ptr) {
; Test VLLEBRZG.
define <2 x i64> @f5(ptr %ptr) {
; CHECK-LABEL: f5:
-; CHECK: vllebrzg %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vllebrzg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %val)
%ret = insertelement <2 x i64> zeroinitializer, i64 %swap, i32 0
@@ -67,8 +73,9 @@ define <2 x i64> @f5(ptr %ptr) {
; Test VLLEBRZG using a vector bswap.
define <2 x i64> @f6(ptr %ptr) {
; CHECK-LABEL: f6:
-; CHECK: vllebrzg %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vllebrzg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i64, ptr %ptr
%insert = insertelement <2 x i64> zeroinitializer, i64 %val, i32 0
%ret = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %insert)
@@ -78,8 +85,9 @@ define <2 x i64> @f6(ptr %ptr) {
; Test VLLEBRZE.
define <4 x i32> @f7(ptr %ptr) {
; CHECK-LABEL: f7:
-; CHECK: vllebrze %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vllebrze %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %val)
%ret = insertelement <4 x i32> zeroinitializer, i32 %swap, i32 0
@@ -89,8 +97,9 @@ define <4 x i32> @f7(ptr %ptr) {
; Test VLLEBRZE using a vector bswap.
define <4 x i32> @f8(ptr %ptr) {
; CHECK-LABEL: f8:
-; CHECK: vllebrze %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vllebrze %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i32, ptr %ptr
%insert = insertelement <4 x i32> zeroinitializer, i32 %val, i32 0
%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %insert)
@@ -100,8 +109,9 @@ define <4 x i32> @f8(ptr %ptr) {
; Test VLLEBRZH with the highest in-range offset.
define <8 x i16> @f9(ptr %base) {
; CHECK-LABEL: f9:
-; CHECK: vllebrzh %v24, 4094(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vllebrzh %v24, 4094(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i16, ptr %base, i64 2047
%val = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %val)
@@ -112,8 +122,10 @@ define <8 x i16> @f9(ptr %base) {
; Test VLLEBRZH with the next highest offset.
define <8 x i16> @f10(ptr %base) {
; CHECK-LABEL: f10:
-; CHECK-NOT: vllebrzh %v24, 4096(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vllebrzh %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i16, ptr %base, i64 2048
%val = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %val)
@@ -124,9 +136,10 @@ define <8 x i16> @f10(ptr %base) {
; Test that VLLEBRZH allows an index.
define <8 x i16> @f11(ptr %base, i64 %index) {
; CHECK-LABEL: f11:
-; CHECK: sllg [[REG:%r[1-5]]], %r3, 1
-; CHECK: vllebrzh %v24, 0([[REG]],%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r1, %r3, 1
+; CHECK-NEXT: vllebrzh %v24, 0(%r1,%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i16, ptr %base, i64 %index
%val = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %val)
diff --git a/llvm/test/CodeGen/SystemZ/vec-bswap-06.ll b/llvm/test/CodeGen/SystemZ/vec-bswap-06.ll
index b37a5da77c897..2b71826109381 100644
--- a/llvm/test/CodeGen/SystemZ/vec-bswap-06.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-bswap-06.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test insertions of byte-swapped memory values into a nonzero index of an undef.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
@@ -12,8 +13,9 @@ declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
; Test v8i16 insertion into an undef, with an arbitrary index.
define <8 x i16> @f1(ptr %ptr) {
; CHECK-LABEL: f1:
-; CHECK: vlbrreph %v24, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrreph %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %val)
%ret = insertelement <8 x i16> undef, i16 %swap, i32 5
@@ -23,8 +25,9 @@ define <8 x i16> @f1(ptr %ptr) {
; Test v8i16 insertion into an undef, using a vector bswap.
define <8 x i16> @f2(ptr %ptr) {
; CHECK-LABEL: f2:
-; CHECK: vlbrreph %v24, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrreph %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i16, ptr %ptr
%insert = insertelement <8 x i16> undef, i16 %val, i32 5
%ret = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %insert)
@@ -34,8 +37,9 @@ define <8 x i16> @f2(ptr %ptr) {
; Test v4i32 insertion into an undef, with an arbitrary index.
define <4 x i32> @f3(ptr %ptr) {
; CHECK-LABEL: f3:
-; CHECK: vlbrrepf %v24, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %val)
%ret = insertelement <4 x i32> undef, i32 %swap, i32 2
@@ -45,8 +49,9 @@ define <4 x i32> @f3(ptr %ptr) {
; Test v4i32 insertion into an undef, using a vector bswap.
define <4 x i32> @f4(ptr %ptr) {
; CHECK-LABEL: f4:
-; CHECK: vlbrrepf %v24, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i32, ptr %ptr
%insert = insertelement <4 x i32> undef, i32 %val, i32 2
%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %insert)
@@ -56,8 +61,9 @@ define <4 x i32> @f4(ptr %ptr) {
; Test v2i64 insertion into an undef, with an arbitrary index.
define <2 x i64> @f5(ptr %ptr) {
; CHECK-LABEL: f5:
-; CHECK: vlbrrepg %v24, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %val)
%ret = insertelement <2 x i64> undef, i64 %swap, i32 1
@@ -67,8 +73,9 @@ define <2 x i64> @f5(ptr %ptr) {
; Test v2i64 insertion into an undef, using a vector bwap.
define <2 x i64> @f6(ptr %ptr) {
; CHECK-LABEL: f6:
-; CHECK: vlbrrepg %v24, 0(%r2)
-; CHECK-NEXT: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%val = load i64, ptr %ptr
%insert = insertelement <2 x i64> undef, i64 %val, i32 1
%ret = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %insert)
diff --git a/llvm/test/CodeGen/SystemZ/vec-bswap-07.ll b/llvm/test/CodeGen/SystemZ/vec-bswap-07.ll
index d9f1f361e658c..8123de1872db3 100644
--- a/llvm/test/CodeGen/SystemZ/vec-bswap-07.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-bswap-07.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test replications of a byte-swapped scalar memory value.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
@@ -12,8 +13,9 @@ declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
; Test a v8i16 replicating load with no offset.
define <8 x i16> @f1(ptr %ptr) {
; CHECK-LABEL: f1:
-; CHECK: vlbrreph %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrreph %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%scalar = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %scalar)
%val = insertelement <8 x i16> undef, i16 %swap, i32 0
@@ -25,8 +27,9 @@ define <8 x i16> @f1(ptr %ptr) {
; Test a v8i16 replicating load with the maximum in-range offset.
define <8 x i16> @f2(ptr %base) {
; CHECK-LABEL: f2:
-; CHECK: vlbrreph %v24, 4094(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrreph %v24, 4094(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i16, ptr %base, i64 2047
%scalar = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %scalar)
@@ -39,9 +42,10 @@ define <8 x i16> @f2(ptr %base) {
; Test a v8i16 replicating load with the first out-of-range offset.
define <8 x i16> @f3(ptr %base) {
; CHECK-LABEL: f3:
-; CHECK: aghi %r2, 4096
-; CHECK: vlbrreph %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlbrreph %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i16, ptr %base, i64 2048
%scalar = load i16, ptr %ptr
%swap = call i16 @llvm.bswap.i16(i16 %scalar)
@@ -54,8 +58,9 @@ define <8 x i16> @f3(ptr %base) {
; Test a v8i16 replicating load using a vector bswap.
define <8 x i16> @f4(ptr %ptr) {
; CHECK-LABEL: f4:
-; CHECK: vlbrreph %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrreph %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%scalar = load i16, ptr %ptr
%val = insertelement <8 x i16> undef, i16 %scalar, i32 0
%rep = shufflevector <8 x i16> %val, <8 x i16> undef,
@@ -67,8 +72,9 @@ define <8 x i16> @f4(ptr %ptr) {
; Test a v4i32 replicating load with no offset.
define <4 x i32> @f5(ptr %ptr) {
; CHECK-LABEL: f5:
-; CHECK: vlbrrepf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%scalar = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %scalar)
%val = insertelement <4 x i32> undef, i32 %swap, i32 0
@@ -80,8 +86,9 @@ define <4 x i32> @f5(ptr %ptr) {
; Test a v4i32 replicating load with the maximum in-range offset.
define <4 x i32> @f6(ptr %base) {
; CHECK-LABEL: f6:
-; CHECK: vlbrrepf %v24, 4092(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepf %v24, 4092(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %base, i64 1023
%scalar = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %scalar)
@@ -94,9 +101,10 @@ define <4 x i32> @f6(ptr %base) {
; Test a v4i32 replicating load with the first out-of-range offset.
define <4 x i32> @f7(ptr %base) {
; CHECK-LABEL: f7:
-; CHECK: aghi %r2, 4096
-; CHECK: vlbrrepf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlbrrepf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %base, i64 1024
%scalar = load i32, ptr %ptr
%swap = call i32 @llvm.bswap.i32(i32 %scalar)
@@ -109,8 +117,9 @@ define <4 x i32> @f7(ptr %base) {
; Test a v4i32 replicating load using a vector bswap.
define <4 x i32> @f8(ptr %ptr) {
; CHECK-LABEL: f8:
-; CHECK: vlbrrepf %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepf %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%scalar = load i32, ptr %ptr
%val = insertelement <4 x i32> undef, i32 %scalar, i32 0
%rep = shufflevector <4 x i32> %val, <4 x i32> undef,
@@ -122,8 +131,9 @@ define <4 x i32> @f8(ptr %ptr) {
; Test a v2i64 replicating load with no offset.
define <2 x i64> @f9(ptr %ptr) {
; CHECK-LABEL: f9:
-; CHECK: vlbrrepg %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%scalar = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %scalar)
%val = insertelement <2 x i64> undef, i64 %swap, i32 0
@@ -135,8 +145,9 @@ define <2 x i64> @f9(ptr %ptr) {
; Test a v2i64 replicating load with the maximum in-range offset.
define <2 x i64> @f10(ptr %base) {
; CHECK-LABEL: f10:
-; CHECK: vlbrrepg %v24, 4088(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepg %v24, 4088(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %base, i32 511
%scalar = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %scalar)
@@ -149,9 +160,10 @@ define <2 x i64> @f10(ptr %base) {
; Test a v2i64 replicating load with the first out-of-range offset.
define <2 x i64> @f11(ptr %base) {
; CHECK-LABEL: f11:
-; CHECK: aghi %r2, 4096
-; CHECK: vlbrrepg %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aghi %r2, 4096
+; CHECK-NEXT: vlbrrepg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %base, i32 512
%scalar = load i64, ptr %ptr
%swap = call i64 @llvm.bswap.i64(i64 %scalar)
@@ -164,8 +176,9 @@ define <2 x i64> @f11(ptr %base) {
; Test a v2i64 replicating load using a vector bswap.
define <2 x i64> @f12(ptr %ptr) {
; CHECK-LABEL: f12:
-; CHECK: vlbrrepg %v24, 0(%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: vlbrrepg %v24, 0(%r2)
+; CHECK-NEXT: br %r14
%scalar = load i64, ptr %ptr
%val = insertelement <2 x i64> undef, i64 %scalar, i32 0
%rep = shufflevector <2 x i64> %val, <2 x i64> undef,
@@ -177,9 +190,10 @@ define <2 x i64> @f12(ptr %ptr) {
; Test a v8i16 replicating load with an index.
define <8 x i16> @f13(ptr %base, i64 %index) {
; CHECK-LABEL: f13:
-; CHECK: sllg [[REG:%r[1-5]]], %r3, 1
-; CHECK: vlbrreph %v24, 2046([[REG]],%r2)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sllg %r1, %r3, 1
+; CHECK-NEXT: vlbrreph %v24, 2046(%r1,%r2)
+; CHECK-NEXT: br %r14
%ptr1 = getelementptr i16, ptr %base, i64 %index
%ptr = getelementptr i16, ptr %ptr1, i64 1023
%scalar = load i16, ptr %ptr
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-12.ll b/llvm/test/CodeGen/SystemZ/vec-perm-12.ll
index c6af5d051b87a..b59eafaf0768b 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-12.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-12.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test inserting a truncated value into a vector element
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | \
@@ -7,28 +8,21 @@
define <4 x i32> @f1(<4 x i32> %x, i64 %y) {
; CHECK-CODE-LABEL: f1:
-; CHECK-CODE-DAG: vlvgf [[ELT:%v[0-9]+]], %r2, 0
-; CHECK-CODE-DAG: larl [[REG:%r[0-5]]],
-; CHECK-CODE-DAG: vl [[MASK:%v[0-9]+]], 0([[REG]])
-; CHECK-CODE: vperm %v24, %v24, [[ELT]], [[MASK]]
-; CHECK-CODE: br %r14
+; CHECK-CODE: # %bb.0:
+; CHECK-CODE-NEXT: larl %r1, .LCPI0_0
+; CHECK-CODE-NEXT: vl %v1, 0(%r1), 3
+; CHECK-CODE-NEXT: vlvgf %v0, %r2, 0
+; CHECK-CODE-NEXT: vperm %v24, %v24, %v0, %v1
+; CHECK-CODE-NEXT: br %r14
+;
+; CHECK-VECTOR-LABEL: f1:
+; CHECK-VECTOR: # %bb.0:
+; CHECK-VECTOR-NEXT: larl %r1, .LCPI0_0
+; CHECK-VECTOR-NEXT: vl %v1, 0(%r1), 3
+; CHECK-VECTOR-NEXT: vlvgf %v0, %r2, 0
+; CHECK-VECTOR-NEXT: vperm %v24, %v24, %v0, %v1
+; CHECK-VECTOR-NEXT: br %r14
-; CHECK-VECTOR: .byte 12
-; CHECK-VECTOR-NEXT: .byte 13
-; CHECK-VECTOR-NEXT: .byte 14
-; CHECK-VECTOR-NEXT: .byte 15
-; CHECK-VECTOR-NEXT: .byte 8
-; CHECK-VECTOR-NEXT: .byte 9
-; CHECK-VECTOR-NEXT: .byte 10
-; CHECK-VECTOR-NEXT: .byte 11
-; CHECK-VECTOR-NEXT: .byte 4
-; CHECK-VECTOR-NEXT: .byte 5
-; CHECK-VECTOR-NEXT: .byte 6
-; CHECK-VECTOR-NEXT: .byte 7
-; CHECK-VECTOR-NEXT: .byte 16
-; CHECK-VECTOR-NEXT: .byte 17
-; CHECK-VECTOR-NEXT: .byte 18
-; CHECK-VECTOR-NEXT: .byte 19
%elt0 = extractelement <4 x i32> %x, i32 3
%elt1 = extractelement <4 x i32> %x, i32 2
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