[PATCH] D152948: [RISCV] Refactor how we create separate instructions for F and Zfinx. NFC
    Shao-Ce SUN via Phabricator via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Wed Jun 14 14:32:54 PDT 2023
    
    
  
sunshaoce added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:442-447
 multiclass PatSetCC_m<SDPatternOperator OpNode, CondCode Cond,
-                      RVInst Inst, list<ExtInfo_r> Exts> {
-  foreach Ext = Exts in
-    let Predicates = Ext.Predicates in
-    def Ext.Suffix : PatSetCC<Ext.Reg, OpNode, Cond,
-                              !cast<RVInst>(Inst#Ext.Suffix)>;
+                      RVInst Inst, ExtInfo Ext, DAGOperand Reg> {
+  let Predicates = Ext.Predicates in
+  def Ext.Suffix : PatSetCC<Reg, OpNode, Cond,
+                            !cast<RVInst>(Inst#Ext.Suffix)>;
 }
----------------
I have a suggestion that may not be entirely accurate.
We can add a `DefaultTy` in the `class ExtInfo`. Then, in `PatSetCC_m`, we can replace `PatSetCC<Reg` with `PatSetCC<Ext.DefaultTy`, so that we don't need to pass `Ext` and `Reg` every time.
This approach could be applied to other classes, especially those that only require passing a single `Reg`.
Repository:
  rG LLVM Github Monorepo
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  https://reviews.llvm.org/D152948/new/
https://reviews.llvm.org/D152948
    
    
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