[PATCH] D152954: [RISCV] Treat __riscv_vsetvl_*(-1) as vlmax.

[Craig Topper via Phabricator via llvm-commits]

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We already treat -1 passed to instruction intrinsics as vlmax, this
make vsetvli consistent.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152954

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll


Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
+++ llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
@@ -126,3 +126,12 @@
   %x = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32.iXLen(<vscale x 4 x i32> undef, <vscale x 4 x i32>* %ptr, iXLen %vl1)
   ret <vscale x 4 x i32> %x
 }
+
+define iXLen @test_vsetvli_negone_e8m1(iXLen %avl) nounwind {
+; CHECK-LABEL: test_vsetvli_negone_e8m1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    ret
+  %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen -1, iXLen 0, iXLen 0)
+  ret iXLen %vl
+}
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -583,7 +583,7 @@
 
   SDValue VLOperand;
   unsigned Opcode = RISCV::PseudoVSETVLI;
-  if (VLMax) {
+  if (VLMax || isAllOnesConstant(Node->getOperand(1))) {
     VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT);
     Opcode = RISCV::PseudoVSETVLIX0;
   } else {


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