[PATCH] D152950: [RISCV] Remove fcvt.d.l(u) and fcvt.l(u).d instructions with _IN32X suffix.

[Craig Topper via Phabricator via llvm-commits]

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_IN32X instructions are for Zdinx on RV32 where doubles are split
across 2 registers.

fcvt.d.l(u) and fcvt.l(u).d are RV64 only instructions so we don't
need _IN32X versions of them.

This existed prior to D152948 <https://reviews.llvm.org/D152948>. I have no looked to see how easy
this is to fix without D152948 <https://reviews.llvm.org/D152948>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152950

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoD.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -62,6 +62,7 @@
                          FPR32INX, FPR64IN32X, ?>;
 
 defvar DExts     = [DExt, ZdinxExt, Zdinx32Ext];
+defvar DExtsRV64 = [DExt, ZdinxExt];
 
 //===----------------------------------------------------------------------===//
 // Instructions
@@ -151,6 +152,9 @@
   defm FCVT_D_WU : FPUnaryOp_r_m<0b1101001, 0b00001, 0b000, Ext, Ext.F64Ty, GPR,
                                  "fcvt.d.wu">,
                    Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
+} // foreach Ext = DExts
+
+foreach Ext = DExtsRV64 in {
   defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, Ext, GPR, Ext.F64Ty,
                                     "fcvt.l.d", [IsRV64]>,
                   Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
@@ -166,7 +170,7 @@
   defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, Ext, Ext.F64Ty, GPR,
                                      "fcvt.d.lu", [IsRV64]>,
                    Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
-} // foreach Ext = DExts
+} // foreach Ext = DExtsRV64
 
 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,


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