[PATCH] D152948: [RISCV] How we create separate instructions for F and Zfinx. NFC

Wed Jun 14 12:35:23 PDT 2023

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Previously we had a ExtInfo_rr class that was instantiated for
every combination of types that can appear together along with
their predicates, suffixes, and decoder namespace.

This patch replaces this with a new ExtInfo class that contains
predicates, suffix, namespace, and the f16, f32, and f64 DAGOperands
implied by the predicates. The DAGOperand can be unset if
the predicate is not enough to distinquish it.

At every instruction instantiation we know whether the operands
are GPR, f16, f32, or f64 and can ask the ExtInfo for the relevant
DAGOperand.

The foreach loops of ExtInfo have been moved out of the classes to
be at the top level of the 3 files. This allows the file to pick
the f16/f32/f64 DAGOperand per instruction and pass it down to the
classes separately from the ExtInfo. The ExtInfo still needs to be
passed down to get suffix, predicates, and decoder namespace.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152948

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

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