[PATCH] D152688: [Aarch64] Add Cortex-A510 specific scheduling

[harvin iriawan via Phabricator via llvm-commits]

harviniriawan marked 3 inline comments as done.
harviniriawan added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA510.td:663
+                        "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_(UNDEF_)?[BHSD]$",
+                        "^(UQSUB|UQSUBR)_ZPmZ_(UNDEF_)?[BHSD]$")>;
+
----------------
dmgreen wrote:
> rjj wrote:
> > harviniriawan wrote:
> > > rjj wrote:
> > > > Same as above.
> > > > 
> > > > There are a few other places where the UNDEF patterns don't seem to exist, but before going through them, any reason why you've included these extra UNDEFs here?
> > > I added them because I see from the debug output of machine-scheduler that sometimes it will generate pseudoinstructions with UNDEF* on some benchmarks, which then will pick up the wrong latency information without adding them into the regex. Maybe in the future we should make UNDEF and PSEUDO to always be at the end of the instruction for easier regex matching.
> > Yep, I totally understand that- I was not suggesting their complete removal! It's just that in a few places the regex was matching "fictitious" UNDEFs, which personally I try to avoid.
> > 
> > I agree, in the future UNDEF and PSEUDO could go at the end of the instruction to facilitate their matching.
> I don't have a strong opinion on the loose regexes, but it would be good to model the UNDEF nodes if we can, as those will be the ones seen during scheduling. SVE seemed to be a place where this scheduling model can have a decent benefit.
Perhaps we can revisit this in future patch. I'd also prefer not to add some cryptic UNDEF and PSEUDO if not necessarry


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  https://reviews.llvm.org/D152688/new/

https://reviews.llvm.org/D152688