[llvm] 2c83809 - [NFC] Automatically generate arm64-dagcombiner-dead-indexed-load.ll

Amaury Séchet via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 14 09:28:15 PDT 2023


Author: Amaury Séchet
Date: 2023-06-14T16:28:04Z
New Revision: 2c83809fa8131f33d75bf1956376ad07e25d7169

URL: https://github.com/llvm/llvm-project/commit/2c83809fa8131f33d75bf1956376ad07e25d7169
DIFF: https://github.com/llvm/llvm-project/commit/2c83809fa8131f33d75bf1956376ad07e25d7169.diff

LOG: [NFC] Automatically generate arm64-dagcombiner-dead-indexed-load.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll b/llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll
index efe1e203e2c99..f504aeb4c0223 100644
--- a/llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mcpu=cyclone < %s | FileCheck %s
 target datalayout = "e-i64:64-n32:64-S128"
 target triple = "arm64-apple-ios"
@@ -10,12 +11,11 @@ target triple = "arm64-apple-ios"
 ; This is a read-modify-write of some bifields combined into an i48.  It gets
 ; legalized into i32 and i16 accesses.  Only a single store of zero to the low
 ; i32 part should be live.
-
-; CHECK-LABEL: test:
-; CHECK-NOT: ldr
-; CHECK: str wzr
-; CHECK-NOT: str
 define void @test(ptr nocapture %su) {
+; CHECK-LABEL: test:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    str wzr, [x0, #96]
+; CHECK-NEXT:    ret
 entry:
   %r1 = getelementptr inbounds %"struct.SU", ptr %su, i64 1, i32 5
   %r3 = load i48, ptr %r1, align 8


        


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