[llvm] fcc9fa5 - [RISCV] Reduce the number of ExtInfo_rr permutations in tablegen.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 14 08:47:31 PDT 2023
Author: Craig Topper
Date: 2023-06-14T08:47:23-07:00
New Revision: fcc9fa55a76a009ececfb1656142d3d7b0842489
URL: https://github.com/llvm/llvm-project/commit/fcc9fa55a76a009ececfb1656142d3d7b0842489
DIFF: https://github.com/llvm/llvm-project/commit/fcc9fa55a76a009ececfb1656142d3d7b0842489.diff
LOG: [RISCV] Reduce the number of ExtInfo_rr permutations in tablegen.
Add ExtraPreds parameter to FPUnaryOp_r_frm_m to pass IsRV64 so we
don't need RV64 versions of ExtInfo_rr.
Differential Revision: https://reviews.llvm.org/D152890
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 9d893e990f7b3..741b17a11ea85 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -55,7 +55,6 @@ def FPR64IN32X : RegisterOperand<GPRPF64> {
}
def DExt : ExtInfo<0, [HasStdExtD]>;
-def D64Ext : ExtInfo<0, [HasStdExtD, IsRV64]>;
def ZdinxExt : ExtInfo<1, [HasStdExtZdinx, IsRV64]>;
def Zdinx32Ext : ExtInfo<2, [HasStdExtZdinx, IsRV32]>;
@@ -72,14 +71,12 @@ def DF_IN32X : ExtInfo_rr<Zdinx32Ext, FPR64IN32X, FPR32INX>;
def DX : ExtInfo_rr<DExt, FPR64, GPR>;
def DX_INX : ExtInfo_rr<ZdinxExt, FPR64INX, GPR>;
def DX_IN32X : ExtInfo_rr<Zdinx32Ext, FPR64IN32X, GPR>;
-def DX_64 : ExtInfo_rr<D64Ext, FPR64, GPR>;
def FD : ExtInfo_rr<DExt, FPR32, FPR64>;
def FD_INX : ExtInfo_rr<ZdinxExt, FPR32INX, FPR64INX>;
def FD_IN32X : ExtInfo_rr<Zdinx32Ext, FPR32INX, FPR64IN32X>;
def XD : ExtInfo_rr<DExt, GPR, FPR64>;
def XD_INX : ExtInfo_rr<ZdinxExt, GPR, FPR64INX>;
def XD_IN32X : ExtInfo_rr<Zdinx32Ext, GPR, FPR64IN32X>;
-def XD_64 : ExtInfo_rr<D64Ext, GPR, FPR64>;
defvar DINX = [D, D_INX, D_IN32X];
defvar DDINX = [DD, DD_INX, DD_IN32X];
@@ -87,8 +84,6 @@ defvar DXINX = [DX, DX_INX, DX_IN32X];
defvar DFINX = [DF, DF_INX, DF_IN32X];
defvar FDINX = [FD, FD_INX, FD_IN32X];
defvar XDINX = [XD, XD_INX, XD_IN32X];
-defvar DXIN64X = [DX_64, DX_INX];
-defvar XDIN64X = [XD_64, XD_INX];
//===----------------------------------------------------------------------===//
// Instructions
@@ -165,20 +160,20 @@ defm FCVT_D_W : FPUnaryOp_r_m<0b1101001, 0b00000, 0b000, DXINX, "fcvt.d.w">,
defm FCVT_D_WU : FPUnaryOp_r_m<0b1101001, 0b00001, 0b000, DXINX, "fcvt.d.wu">,
Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
-defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, XDIN64X, "fcvt.l.d">,
+defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, XDINX, "fcvt.l.d", [IsRV64]>,
Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
-defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, XDIN64X, "fcvt.lu.d">,
+defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, XDINX, "fcvt.lu.d", [IsRV64]>,
Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>;
let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">,
Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;
-defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, DXIN64X, "fcvt.d.l">,
+defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, DXINX, "fcvt.d.l", [IsRV64]>,
Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
-defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, DXIN64X, "fcvt.d.lu">,
+defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, DXINX, "fcvt.d.lu", [IsRV64]>,
Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>;
let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 3ae6681bbc82d..115cd67c4b459 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -115,9 +115,7 @@ class ExtInfo_rr<ExtInfo ext, DAGOperand rdty, DAGOperand rs1ty> {
}
def FExt : ExtInfo<0, [HasStdExtF]>;
-def F64Ext : ExtInfo<0, [HasStdExtF, IsRV64]>;
def ZfinxExt : ExtInfo<1, [HasStdExtZfinx]>;
-def Zfinx64Ext : ExtInfo<1, [HasStdExtZfinx, IsRV64]>;
def F : ExtInfo_r<FExt, FPR32>;
def F_INX : ExtInfo_r<ZfinxExt, FPR32INX>;
@@ -126,19 +124,13 @@ def FF : ExtInfo_rr<FExt, FPR32, FPR32>;
def FF_INX : ExtInfo_rr<ZfinxExt, FPR32INX, FPR32INX>;
def FX : ExtInfo_rr<FExt, FPR32, GPR>;
def FX_INX : ExtInfo_rr<ZfinxExt, FPR32INX, GPR>;
-def FX_64 : ExtInfo_rr<F64Ext, FPR32, GPR>;
-def FX_INX_64 : ExtInfo_rr<Zfinx64Ext, FPR32INX, GPR>;
def XF : ExtInfo_rr<FExt, GPR, FPR32>;
-def XF_64 : ExtInfo_rr<F64Ext, GPR, FPR32>;
def XF_INX : ExtInfo_rr<ZfinxExt, GPR, FPR32INX>;
-def XF_INX_64 : ExtInfo_rr<Zfinx64Ext, GPR, FPR32INX>;
defvar FINX = [F, F_INX];
defvar FFINX = [FF, FF_INX];
defvar FXINX = [FX, FX_INX];
defvar XFINX = [XF, XF_INX];
-defvar XFIN64X = [XF_64, XF_INX_64];
-defvar FXIN64X = [FX_64, FX_INX_64];
// Floating-point rounding mode
@@ -246,9 +238,11 @@ class FPUnaryOp_r_frm<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,
let rs2 = rs2val;
}
multiclass FPUnaryOp_r_frm_m<bits<7> funct7, bits<5> rs2val,
- list<ExtInfo_rr> Exts, string opcodestr> {
+ list<ExtInfo_rr> Exts, string opcodestr,
+ list<Predicate> ExtraPreds = []> {
foreach Ext = Exts in
- let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
+ let Predicates = !listconcat(Ext.Predicates, ExtraPreds),
+ DecoderNamespace = Ext.Space in
def Ext.Suffix : FPUnaryOp_r_frm<funct7, rs2val, Ext.RdTy, Ext.Rs1Ty,
opcodestr>;
}
@@ -356,16 +350,16 @@ let Predicates = [HasStdExtF], mayRaiseFPException = 0 in
def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
-defm FCVT_L_S : FPUnaryOp_r_frm_m<0b1100000, 0b00010, XFIN64X, "fcvt.l.s">,
+defm FCVT_L_S : FPUnaryOp_r_frm_m<0b1100000, 0b00010, XFINX, "fcvt.l.s", [IsRV64]>,
Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>;
-defm FCVT_LU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00011, XFIN64X, "fcvt.lu.s">,
+defm FCVT_LU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00011, XFINX, "fcvt.lu.s", [IsRV64]>,
Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]>;
-defm FCVT_S_L : FPUnaryOp_r_frm_m<0b1101000, 0b00010, FXIN64X, "fcvt.s.l">,
+defm FCVT_S_L : FPUnaryOp_r_frm_m<0b1101000, 0b00010, FXINX, "fcvt.s.l", [IsRV64]>,
Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>;
-defm FCVT_S_LU : FPUnaryOp_r_frm_m<0b1101000, 0b00011, FXIN64X, "fcvt.s.lu">,
+defm FCVT_S_LU : FPUnaryOp_r_frm_m<0b1101000, 0b00011, FXINX, "fcvt.s.lu", [IsRV64]>,
Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index b000f18c57728..a21fc148d9bd9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -39,11 +39,9 @@ def FPR16INX : RegisterOperand<GPRF16> {
}
def ZfhExt : ExtInfo<0, [HasStdExtZfh]>;
-def Zfh64Ext : ExtInfo<0, [HasStdExtZfh, IsRV64]>;
def ZfhminExt : ExtInfo<0, [HasStdExtZfhOrZfhmin]>;
def ZhinxExt : ExtInfo<1, [HasStdExtZhinx]>;
def ZhinxminExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin]>;
-def Zhinx64Ext : ExtInfo<1, [HasStdExtZhinx, IsRV64]>;
def ZfhminDExt : ExtInfo<0, [HasStdExtZfhOrZfhmin, HasStdExtD]>;
def ZhinxminZdinxExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64]>;
@@ -58,10 +56,6 @@ def XH : ExtInfo_rr<ZfhExt, GPR, FPR16>;
def XH_INX : ExtInfo_rr<ZhinxExt, GPR, FPR16INX>;
def HX : ExtInfo_rr<ZfhExt, FPR16, GPR>;
def HX_INX : ExtInfo_rr<ZhinxExt, FPR16INX, GPR>;
-def XH_64 : ExtInfo_rr<Zfh64Ext, GPR, FPR16>;
-def HX_64 : ExtInfo_rr<Zfh64Ext, FPR16, GPR>;
-def XH_INX_64 : ExtInfo_rr<Zhinx64Ext, GPR, FPR16INX>;
-def HX_INX_64 : ExtInfo_rr<Zhinx64Ext, FPR16INX, GPR>;
def HFmin : ExtInfo_rr<ZfhminExt, FPR16, FPR32>;
def HF_INXmin : ExtInfo_rr<ZhinxminExt, FPR16INX, FPR32INX>;
def HF_INX : ExtInfo_rr<ZhinxExt, FPR16INX, FPR32INX>;
@@ -79,8 +73,6 @@ defvar HINX = [H, H_INX];
defvar HHINX = [HH, HH_INX];
defvar XHINX = [XH, XH_INX];
defvar HXINX = [HX, HX_INX];
-defvar XHIN64X = [XH_64, XH_INX_64];
-defvar HXIN64X = [HX_64, HX_INX_64];
defvar HFINXmin = [HFmin, HF_INXmin];
defvar FHINXmin = [FHmin, FH_INXmin];
defvar DHINXmin = [DHmin, DH_INXmin, DH_INX32min];
@@ -171,16 +163,16 @@ let mayRaiseFPException = 0 in
defm FCLASS_H : FPUnaryOp_r_m<0b1110010, 0b00000, 0b001, XHINX, "fclass.h">,
Sched<[WriteFClass16, ReadFClass16]>;
-defm FCVT_L_H : FPUnaryOp_r_frm_m<0b1100010, 0b00010, XHIN64X, "fcvt.l.h">,
+defm FCVT_L_H : FPUnaryOp_r_frm_m<0b1100010, 0b00010, XHINX, "fcvt.l.h", [IsRV64]>,
Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>;
-defm FCVT_LU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00011, XHIN64X, "fcvt.lu.h">,
+defm FCVT_LU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00011, XHINX, "fcvt.lu.h", [IsRV64]>,
Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>;
-defm FCVT_H_L : FPUnaryOp_r_frm_m<0b1101010, 0b00010, HXIN64X, "fcvt.h.l">,
+defm FCVT_H_L : FPUnaryOp_r_frm_m<0b1101010, 0b00010, HXINX, "fcvt.h.l", [IsRV64]>,
Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>;
-defm FCVT_H_LU : FPUnaryOp_r_frm_m<0b1101010, 0b00011, HXIN64X, "fcvt.h.lu">,
+defm FCVT_H_LU : FPUnaryOp_r_frm_m<0b1101010, 0b00011, HXINX, "fcvt.h.lu", [IsRV64]>,
Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>;
defm FCVT_H_D : FPUnaryOp_r_frm_m<0b0100010, 0b00001, HDINXmin, "fcvt.h.d">,
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