[PATCH] D151894: [AArch64] Neoverse V2 scheduling model

[Ricardo Jesus via Phabricator via llvm-commits]

rjj marked an inline comment as done.
rjj added a comment.

In D151894#4421115 <https://reviews.llvm.org/D151894#4421115>, @dmgreen wrote:

> Thanks. The new test looks good.
>
> The details in the model looks good from what I have checked. I think it is worth getting this in we can iterate if needed from there if needed.
>
> LGTM Thanks.

Perfect, thanks very much!



================
Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td:1026-1027
+// SDIV, UDIV
+def : SchedAlias<WriteID32,  V2Write_12cyc_1M0>;
+def : SchedAlias<WriteID64,  V2Write_20cyc_1M0>;
+
----------------
dmgreen wrote:
> rjj wrote:
> > dmgreen wrote:
> > > rjj wrote:
> > > > dmgreen wrote:
> > > > > 12 and 20 are worst-case times. Would a value more in the middle of the range be better?
> > > > Sure, so maybe 8 and 12 respectively? Do you have a better suggestion? What about the throughput, 1/8 and 1/12?
> > > It is the let ResourceCycles = [12] that will define the throughput. If the instruction uses the V2UnitM0 pipeline for multiple cycles, then other operations that use the same pipeline (for example other divs) will not be able to issue.
> > Yep, sorry, I meant if 8 and 12 seemed like reasonable latencies for DIVs, compared to the worst-case times of 12 and 20.
> Honestly I'm not sure what the profile of latencies would look like, for common values of divides. I'm happy to stick with the current values if we don't see them causing problems, and we can adjust them in the future if we need to.
Cool, I'll leave the worst-case ones then and we can revisit this later if need be.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151894/new/

https://reviews.llvm.org/D151894