[PATCH] D152892: [AMDGPU] Remove return VGPRs from callee save list

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added a comment.

In D152892#4421104 <https://reviews.llvm.org/D152892#4421104>, @sebastian-ne wrote:

> LGTM if there are no further concerns from @cdevadas.

No other concerns.



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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1521
         MFI->allocateWWMSpill(MF, MI.getOperand(1).getReg());
+      else if (MI.getOpcode() == AMDGPU::SI_RETURN ||
+               MI.getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
----------------
sebastian-ne wrote:
> cdevadas wrote:
> > I assume this is only a short-term fix until revising the gfx ABI to move return VGPRs into the scratch regs range to avoid the CSR spills/restores.
> I think this is a long-term solution :)
> Callee-saves have the striped pattern, which is good and what we want.
> But if a function decides that it wants to return a lot of values – and they fit into registers – then why not use these registers for the return value, even if they are callee-save (just that they cannot be callee-save for this function return).
Ok.



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  https://reviews.llvm.org/D152892/new/

https://reviews.llvm.org/D152892