[PATCH] D152915: [RISCV] Add support for XCVbitmanip extension in CV32E40P

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Implement XCVbitmanip intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, @simoncook

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152915

Files:
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCVbitmanip.td
  llvm/test/MC/RISCV/corev/bitmanip/bclr-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/bclr.s
  llvm/test/MC/RISCV/corev/bitmanip/bclrr-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/bclrr.s
  llvm/test/MC/RISCV/corev/bitmanip/bitrev-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/bitrev.s
  llvm/test/MC/RISCV/corev/bitmanip/bset-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/bset.s
  llvm/test/MC/RISCV/corev/bitmanip/bsetr-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/bsetr.s
  llvm/test/MC/RISCV/corev/bitmanip/clb-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/clb.s
  llvm/test/MC/RISCV/corev/bitmanip/cnt-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/cnt.s
  llvm/test/MC/RISCV/corev/bitmanip/extract-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/extract.s
  llvm/test/MC/RISCV/corev/bitmanip/extractr-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/extractr.s
  llvm/test/MC/RISCV/corev/bitmanip/extractu-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/extractu.s
  llvm/test/MC/RISCV/corev/bitmanip/extractur-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/extractur.s
  llvm/test/MC/RISCV/corev/bitmanip/ff1-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/ff1.s
  llvm/test/MC/RISCV/corev/bitmanip/fl1-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/fl1.s
  llvm/test/MC/RISCV/corev/bitmanip/insert-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/insert.s
  llvm/test/MC/RISCV/corev/bitmanip/insertr-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/insertr.s
  llvm/test/MC/RISCV/corev/bitmanip/ror-invalid.s
  llvm/test/MC/RISCV/corev/bitmanip/ror.s

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