[llvm] 024e540 - [AMDGPU][AsmParser][NFC] Get rid of custom default operand handlers.
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 14 04:11:18 PDT 2023
Author: Ivan Kosarev
Date: 2023-06-14T12:10:56+01:00
New Revision: 024e5408969fe52db567c2a4e02fb15487c30ba0
URL: https://github.com/llvm/llvm-project/commit/024e5408969fe52db567c2a4e02fb15487c30ba0
DIFF: https://github.com/llvm/llvm-project/commit/024e5408969fe52db567c2a4e02fb15487c30ba0.diff
LOG: [AMDGPU][AsmParser][NFC] Get rid of custom default operand handlers.
Removes the need to add and remove them manually depending on whether
they are used in cvt*() functions. Also removes the compiler warnings
about unused handlers when it happens to be the case.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D151688
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 91c6e8ba4f880..e8a725b656607 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -123,21 +123,27 @@ def FMA : Predicate<"Subtarget->hasFMA()">;
def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
-class CustomOperandClass<string name, bit optional, string parserMethod>
+class CustomOperandClass<string name, bit optional, string parserMethod,
+ string defaultMethod>
: AsmOperandClass {
let Name = name;
let PredicateMethod = "is"#name;
let ParserMethod = parserMethod;
let RenderMethod = "addImmOperands";
let IsOptional = optional;
- let DefaultMethod = "default"#name;
+ let DefaultMethod = defaultMethod;
}
class CustomOperandProps<bit optional = 0, string name = NAME> {
+ string ImmTy = "ImmTy"#name;
string ParserMethod = "parse"#name;
+ string DefaultValue = "0";
+ string DefaultMethod = "[this]() { return "#
+ "AMDGPUOperand::CreateImm(this, "#DefaultValue#", SMLoc(), "#
+ "AMDGPUOperand::"#ImmTy#"); }";
string PrintMethod = "print"#name;
AsmOperandClass ParserMatchClass =
- CustomOperandClass<name, optional, ParserMethod>;
+ CustomOperandClass<name, optional, ParserMethod, DefaultMethod>;
string OperandType = "OPERAND_IMMEDIATE";
}
@@ -147,6 +153,7 @@ class CustomOperand<ValueType type, bit optional = 0, string name = NAME>
class ImmOperand<ValueType type, string name, bit optional = 0,
string printer = "print"#name>
: CustomOperand<type, optional, name> {
+ let ImmTy = "ImmTyNone";
let ParserMethod = "";
let PrintMethod = printer;
}
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 6205678f48cd3..91413945add8c 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1754,13 +1754,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true); }
void cvtMtbuf(MCInst &Inst, const OperandVector &Operands);
- AMDGPUOperand::Ptr defaultCPol() const;
-
- AMDGPUOperand::Ptr defaultSMRDOffset8() const;
- AMDGPUOperand::Ptr defaultSMEMOffset() const;
- AMDGPUOperand::Ptr defaultSMEMOffsetMod() const;
- AMDGPUOperand::Ptr defaultFlatOffset() const;
-
OperandMatchResultTy parseOModSI(OperandVector &Operands);
void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
@@ -1792,10 +1785,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);
int64_t parseDPPCtrlSel(StringRef Ctrl);
int64_t parseDPPCtrlPerm();
- AMDGPUOperand::Ptr defaultDppRowMask() const;
- AMDGPUOperand::Ptr defaultDppBankMask() const;
- AMDGPUOperand::Ptr defaultDppBoundCtrl() const;
- AMDGPUOperand::Ptr defaultDppFI() const;
void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {
cvtDPP(Inst, Operands, true);
@@ -1819,15 +1808,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool SkipDstVcc = false,
bool SkipSrcVcc = false);
- AMDGPUOperand::Ptr defaultBLGP() const;
- AMDGPUOperand::Ptr defaultCBSZ() const;
- AMDGPUOperand::Ptr defaultABID() const;
-
OperandMatchResultTy parseEndpgm(OperandVector &Operands);
- AMDGPUOperand::Ptr defaultEndpgm() const;
- AMDGPUOperand::Ptr defaultWaitVDST() const;
- AMDGPUOperand::Ptr defaultWaitEXP() const;
OperandMatchResultTy parseVOPD(OperandVector &Operands);
};
@@ -7736,10 +7718,6 @@ AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {
// mubuf
//===----------------------------------------------------------------------===//
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultCPol() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyCPol);
-}
-
void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
const OperandVector &Operands,
bool IsAtomic) {
@@ -7979,23 +7957,6 @@ bool AMDGPUOperand::isSMRDLiteralOffset() const {
return isImmLiteral() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
}
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDOffset8() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyNone);
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMEMOffset() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc());
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMEMOffsetMod() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(),
- AMDGPUOperand::ImmTySMEMOffsetMod);
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultFlatOffset() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
-}
-
//===----------------------------------------------------------------------===//
// vop3
//===----------------------------------------------------------------------===//
@@ -8709,26 +8670,6 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
return MatchOperand_Success;
}
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppRowMask() const {
- return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppRowMask);
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultEndpgm() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyEndpgm);
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppBankMask() const {
- return AMDGPUOperand::CreateImm(this, 0xf, SMLoc(), AMDGPUOperand::ImmTyDppBankMask);
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppBoundCtrl() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppBoundCtrl);
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDppFI() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppFI);
-}
-
void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
bool IsDPP8) {
OptionalImmIndexMap OptionalIdx;
@@ -9084,22 +9025,6 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
}
}
-//===----------------------------------------------------------------------===//
-// mAI
-//===----------------------------------------------------------------------===//
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultBLGP() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyBLGP);
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultCBSZ() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyCBSZ);
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultABID() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyABID);
-}
-
/// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser() {
RegisterMCAsmParser<AMDGPUAsmParser> A(getTheAMDGPUTarget());
@@ -9221,10 +9146,6 @@ bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }
// LDSDIR
//===----------------------------------------------------------------------===//
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultWaitVDST() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyWaitVDST);
-}
-
bool AMDGPUOperand::isWaitVDST() const {
return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());
}
@@ -9233,10 +9154,6 @@ bool AMDGPUOperand::isWaitVDST() const {
// VINTERP
//===----------------------------------------------------------------------===//
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultWaitEXP() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyWaitEXP);
-}
-
bool AMDGPUOperand::isWaitEXP() const {
return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm());
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index c9272b87a8370..ec9df71ebff84 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1113,19 +1113,17 @@ def SDWAVopcDst : BoolRC {
class NamedIntOperand<ValueType Type, string Prefix, string Name = NAME,
string ConvertMethod = "nullptr">
: CustomOperand<Type, 1, Name> {
- string ImmTy = "AMDGPUOperand::ImmTy"#Name;
let ParserMethod =
"[this](OperandVector &Operands) -> OperandMatchResultTy { "#
- "return parseIntWithPrefix(\""#Prefix#"\", Operands, "#ImmTy#", "#
- ConvertMethod#"); }";
+ "return parseIntWithPrefix(\""#Prefix#"\", Operands, "#
+ "AMDGPUOperand::"#ImmTy#", "#ConvertMethod#"); }";
}
class NamedBitOperand<string Id, string Name = NAME>
: CustomOperand<i1, 1, Name> {
- string ImmTy = "AMDGPUOperand::ImmTy"#Name;
let ParserMethod =
"[this](OperandVector &Operands) -> OperandMatchResultTy { "#
- "return parseNamedBit(\""#Id#"\", Operands, "#ImmTy#"); }";
+ "return parseNamedBit(\""#Id#"\", Operands, AMDGPUOperand::"#ImmTy#"); }";
}
class DefaultOperand<CustomOperand Op, int Value>
@@ -1136,21 +1134,21 @@ class DefaultOperand<CustomOperand Op, int Value>
class SDWAOperand<string Id, string Name = NAME>
: CustomOperand<i32, 1, Name> {
- string ImmTy = "AMDGPUOperand::ImmTy"#Name;
let ParserMethod =
"[this](OperandVector &Operands) -> OperandMatchResultTy { "#
- "return parseSDWASel(Operands, \""#Id#"\", "#ImmTy#"); }";
+ "return parseSDWASel(Operands, \""#Id#"\", AMDGPUOperand::"#ImmTy#"); }";
}
class ArrayOperand0<string Id, string Name = NAME>
: OperandWithDefaultOps<i32, (ops (i32 0))>,
CustomOperandProps<1, Name> {
- string ImmTy = "AMDGPUOperand::ImmTy"#Name;
let ParserMethod =
"[this](OperandVector &Operands) -> OperandMatchResultTy { "#
- "return parseOperandArrayWithPrefix(\""#Id#"\", Operands, "#ImmTy#"); }";
+ "return parseOperandArrayWithPrefix(\""#Id#"\", Operands, "#
+ "AMDGPUOperand::"#ImmTy#"); }";
}
+let ImmTy = "ImmTyOffset" in
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
def offset : NamedIntOperand<i32, "offset", "Offset">;
def offset0 : NamedIntOperand<i8, "offset0", "Offset0">;
@@ -1202,8 +1200,10 @@ def neg_hi0 : ArrayOperand0<"neg_hi", "NegHi">;
def dpp8 : CustomOperand<i32, 0, "DPP8">;
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;
+let DefaultValue = "0xf" in {
def row_mask : NamedIntOperand<i32, "row_mask", "DppRowMask">;
def bank_mask : NamedIntOperand<i32, "bank_mask", "DppBankMask">;
+}
def bound_ctrl : NamedIntOperand<i1, "bound_ctrl", "DppBoundCtrl",
"[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }">;
def FI : NamedIntOperand<i32, "fi", "DppFI">;
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