[PATCH] D152679: [RISCV] Eliminate the extension of index for vector indexed load/store.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added a comment.

In D152679#4416200 <https://reviews.llvm.org/D152679#4416200>, @sorear wrote:

> Is the SIGN_EXTEND case actually correct?  Vector indexed memory operations always zero-extend the index, and the getelementptr doesn't provide enough information to prove the indices are nonnegative.
>
> I think the best we can do without new metadata is
>
>   vsetvli zero, a1, e8, m1, ta, ma
>   addi a0, a0, -128
>   li a1, -128
>   vxor.vs v9, v9, a1  # vfneg.v can be used for some SEW
>   vsoxei8.v v8, (a0), v9, v0.t

Yes, I change this patch to match only zero_ext.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D152679/new/

https://reviews.llvm.org/D152679