[PATCH] D151414: [RISCV] Add Zvfhmin extension support for llvm RISCV backend.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan marked 3 inline comments as done.
jacquesguan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:857
+      for (MVT VT : F16VecVTs) {
+        setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
+        setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
----------------
michaelmaitland wrote:
> Need an `isTypeLegal` check?
> 
> From the v-spec:
> ```
> When LMUL < SEW/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice. For example, with VLEN=ELEN=32, and SEWMIN=8, an LMUL of 1/8 would only provide four bits of storage in a vector register.
> ```
> 
> Consider the scenario when `VT` is `<vscale x 1 x 16>`. Then LMUL=MF4. If VLEN=ELEN=32 then LMUL=MF4 would only provide 8 bits of storage in a vector register when 16 is needed.
Done, thanks.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vfadd.ll:15
+
+; ZVFMIN: LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vfadd
+
----------------
craig.topper wrote:
> Is there a plan to support this via promotion in a future patch?
Yes, I am working on a patch to do this.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D151414