[PATCH] D152844: [RISCV][InsertVSETVLI] Rework code structure to make reasoning about undefined lanes explicit [NFC]

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.

LGTM with a comment question. Agreed, this is nice to see.



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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:905
   // * The LMUL1 restriction is for machines whose latency may depend on VL.
   // * As above, this is only legal for IMPLICIT_DEF, not TA.
   if (isVSlideInstr(MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
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Does this comment hold? Could it now be improved?


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https://reviews.llvm.org/D152844