[PATCH] D152892: [AMDGPU] Remove return VGPRs from callee save list

[Carl Ritson via Phabricator via llvm-commits]

critson created this revision.
critson added reviewers: sebastian-ne, arsenm, cdevadas, nhaehnle.
Herald added subscribers: foad, kerbowa, hiraditya, tpr, dstuttard, yaxunl, jvesely, kzhuravl.
Herald added a project: All.
critson requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

There is no need to generate spill/restore for registers used in
return value.  This matters for amdgpu_gfx calling convention
where CSR and Ret definitions overlap.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152892

Files:
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp


Index: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -1501,6 +1501,7 @@
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 
+  MachineInstr *ReturnMI = nullptr;
   for (MachineBasicBlock &MBB : MF) {
     for (MachineInstr &MI : MBB) {
       // WRITELANE instructions used for SGPR spills can overwrite the inactive
@@ -1517,6 +1518,19 @@
         MFI->allocateWWMSpill(MF, MI.getOperand(0).getReg());
       else if (MI.getOpcode() == AMDGPU::V_READLANE_B32)
         MFI->allocateWWMSpill(MF, MI.getOperand(1).getReg());
+      else if (MI.getOpcode() == AMDGPU::SI_RETURN ||
+               MI.getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG)
+        ReturnMI = &MI;
+    }
+  }
+
+  // Remove any VGPRs used in the return value these do not need to be saved.
+  // This prevents CSR restore from clobbering return VGPRs.
+  // Note: this assumes all return instructions are of equal.
+  if (ReturnMI) {
+    for (auto &Op : ReturnMI->operands()) {
+      if (Op.isReg())
+        SavedVGPRs.reset(Op.getReg());
     }
   }
 


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